[SI-LIST] Best PDS impedance for package damping
- From: Larry Smith <Larry.Smith@xxxxxxx>
- To: ctwardy@xxxxxxxxxxxxxxxxxx
- Date: Fri, 13 Feb 2004 10:30:33 -0800
(I changed the subject to better reflect the content..)
Craig, Istvan, Steve - "the big V" associated with discrete capacitor
impedance does not cause ASICs to resonate at the die but it can
certainly make it a lot worse. There will always be some level of
inductance in the mounted package that will resonate with the
capacitance in the die (and/or capacitance on the package). Depending
on how the PCB capacitors are chosen, their inductance may (and
usually does) add to that of the package and mount . This will
increase the Q of the resonant circuit and lower the resonant
frequency (bad things).
If PCB capacitors are chosen such that they present a resistive
impedance rather than inductive impedance at the chip/package resonant
frequency, they provide damping and reduce the Q of the resonant
circuit rather than increase it. This is the best you can hope for.
The optimum situation is to have the PCB present the target impedance
at zero phase (resistance) to the resonant circuit. This presents the
maximum damping resistance with acceptable voltage regulation (IR drop
in the PDS resistance).
Sure, it would be nice to have specified ESR capacitors to help us
create the optimum impedance. But I work in a components group.
There is no way we will pay for the added costs, the testing, the
inventory control or deal with the number of unique P/N capacitors
that this would required if there were specified ESR options for each
capacitor value.
On the other hand, the ESR of ceramic capacitors available today is
very predictable. For a particular value of capacitor, we find about
20% ESR variation over the several major capacitor suppliers. We can
live with that! By choosing from a menu of 2 dozen or so capacitors
(three per decade over 5 decades of values) it is easy to present any
impedance you want to the mounted ASIC including a nice flat profile
with frequency. In every case that we have evaluated, this has
resulted in the lowest component cost but does create added
manufacturing complexity with more reels of components around the
"pick and place" equipment. Optimize it any way you want! I know
what I am going to do.
regards,
Larry Smith
Sun Microsystems
Craig Twardy wrote:
> Steve, Istvan;
> "the big V" can also cause ASICs to resonate at the die.
> Usually the significant lossy component (dampening) is the ESR of "the big
> V".
> When this gets small, the ASIC package can become underdamped.
> "the big V" does not have to coincident exactly with the natural resonant
> frequency of the ASIC Package.
> It just needs to be somewhere close (within an octave or two can be
> sufficient).
>
> When this happens the noise seen at the PCB is usually low.
>
> I guess this goes back to a previous thread; without knowing the ASIC
> package
> And die components, power supply decoupling is a crap shoot.
>
>
>
> Craig
>
> -----Original Message-----
> From: Istvan NOVAK [mailto:istvan.novak@xxxxxxxxxxxxxxxx]
> Sent: February 13, 2004 8:27 AM
> To: weirsp@xxxxxxxxxx
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Stack up for EMI reduction,plane resonance and u-str
> ip radiation etc etc
>
>
> Steve,
>
> Well said. Given the fact that there is still hardly any bypass capacitor
> on the market where the designer would have a known range for its ESR,
> selecting the largest value cap in a ceramic case style, and creating a
> single deep V seems to be a good working compromise.
>
> There are two penalties associated with this solution. At low frequencies,
> where the V shape interfaces with the impedance of bigger capacitors, we
> will have to pay a factor of two either in the inductance of the bigger caps
> (need twice as many) or in the capacitance of the ceramic caps creating the
> deep V (if we selected the biggest capacitance in the case style, this also
> means we need twice as many). There is a similar but more severe penalty at
> high frequencies, where these ceramic capacitors interface with the planes,
> let it be thin dielectric -:) or thick dielectric. To sufficiently suppress
> the capacitor-plane resonance and the first few plane modal resonances, the
> cumulative inductance of the parts has to be several times less, which means
> correspondingly more parts. But I agree that given the circumstances this
> is a safe working solution.
>
> I hope sooner than later the industry will demand bypass capacitors with
> specified ESR values (with +- tolerance) where the nominal ESR value can be
> selected from a list, similar to nominal voltage, material, etc.
>
> Regards,
>
> Istvan
>
>
>
> ----- Original Message -----
> From: "steve weir" <weirsp@xxxxxxxxxx>
> To: "Bart Bouma" <bart.bouma@xxxxxxxxx>
> Cc: <si-list@xxxxxxxxxxxxx>; <si-list-bounce@xxxxxxxxxxxxx>;
> <zhang_kun@xxxxxxxxxx>
> Sent: Friday, February 13, 2004 4:47 AM
> Subject: [SI-LIST] Re: Stack up for EMI reduction,plane resonance and u-str
> ip radiation etc etc
>
>
>
>>Bart, I don't know why people fear that big "V". Capacitors by the
>>decade are something that I oppose. I have seen people, including
>>respected consultants mess up capacitors by the decade and blow
>>impedance targets by a factor of 3:1 or more. In the meantime, no
>>parts were saved. There is nothing wrong with an impedance lower than
>>target, and the capacitor count is driven by the requisite inductance
>>to meet the HF intercept. Take the same qty of capacitors using
>>decade spacing, and just substitute the larger value for all of them
>>and the impedance plot is
>
> still
>
>>very well behaved, and the phase doesn't go all over creation.
>>
>>The only argument that anyone could ever try and make for smaller
>>value capacitors that makes any sense to me is the higher ESR of the
>>small values, provided it is high enough to get close to Ztarget that
>>will help damp anti resonance with the planes. In that case, I can
>>see clear to two values of ceramic caps properly chosen, but not by
>>the decade. But, I
>
> have
>
>>yet to see any author who advocates multiple values of MLCCs advocate
>>on the basis of bringing up the ESR. It has always been based on this
>>folklore surrounding some perceived need for a flat impedance curve,
>>that many then blow due to antiresonance.
>>
>>Regards,
>>
>>
>>Steve.
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