Thanks Wolfgang and all, Yes, indeed I haven't thought of fringe capacitance. I don't know if there is an easy analytical way to find out what it will be. The area of the polygon is 1400 sq.mm. The perimeter is 236 mm. The dielectric is FR-4, and the thikness is about 5 mil (0.127mm). The top layer is not a plane and there is not much copper in it, mostly pads and vias. The gap around this polygon separating it from the rest of the plane is 15 mil (0.381mm) wide. The board dimensions are 233x160 mm. Thanks again, /Mikhail ----- Original Message ----- From: wolfgang.maichen@xxxxxxxxxxxx To: Mikhail Matusov Cc: si-list@xxxxxxxxxxxxx ; si-list-bounce@xxxxxxxxxxxxx Sent: Thursday, September 09, 2010 2:11 PM Subject: Re: [SI-LIST] Basic question on power plane capacitance Mikhail, If the polygon isn't very large (~100x) compared to its distance from the ground plane then fringe capacitance will contribute significantly to the total value - i.e. the actual capacitance will be quite a bit higher than what you'd expect from the simple formula for a planar capacitor. In addition, if your dielectric is a low-cost material (e.g. FR-4) its dielctric constant can easily be off by ~10% from the specified value. A 2.5D or 3D field solver can tell you how much total capacitance to expect. One suitable choice would be Sonnet Lite (i.e. the demo version of Sonnet). If you can tell me the size/geometry of your polygon, distance to the ground plane, and dielectric constant of the board material I can run a quick simulation for you. Just to rule out an obvious mistakes, you did take into account that having both a plane below and above the polygon will douple the capacitance compared to just a single pair (polygon and single ground plane)? Forgetting that would immediately explain a mismatch factor of 2. Regards, Wolfgang "Mikhail Matusov" <matusov@xxxxxxxxxxxx> Sent by: si-list-bounce@xxxxxxxxxxxxx 09/09/2010 10:50 AM To <si-list@xxxxxxxxxxxxx> cc Subject [SI-LIST] Basic question on power plane capacitance Hi all, I have a small polygon in a plane layer of a multi-layer PCB. There is a solid ground plane underneath it and the top signal layer above. I have calculated from the basic plane capacitance equation that the plane capacitance for this polygon should be in the range of 420 pF. However, I am measuring 890 pF with one meter and 1 nF with another. I was wondering what am I doing wrong? Thanks, /Mikhail ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu