[SI-LIST] Re: Basic question on power plane capacitance

David,

Yes, there are small BGA pads.

/Mikhail



----- Original Message ----- 
From: "David" <dpalmer@xxxxxxxxxxxxx>
To: "Istvan Novak" <istvan.novak@xxxxxxx>
Cc: "Mikhail Matusov" <matusov@xxxxxxxxxxxx>; "steve weir" 
<weirsi@xxxxxxxxxx>; <wolfgang.maichen@xxxxxxxxxxxx>; 
<si-list@xxxxxxxxxxxxx>
Sent: Friday, September 10, 2010 11:40 AM
Subject: Re: [SI-LIST] Re: Basic question on power plane capacitance


> Are there SMT pads for the ground pins of components on layer 1?
>
>
>
> Istvan Novak wrote:
>> While all the various tolerances mentioned on this thread are possible 
>> contributors to
>> the difference you experience, I would not rule out measurement problem 
>> either. You
>> said you used a simple low-frequency instrument; probably something like 
>> a hand-held
>> DVM with capacitance measurement capability.  Those can sometimes give 
>> very stable,
>> repeatable, but COMPLTELY WRONG readings.  I recently lost a few hours by 
>> debugging
>> a similar scenario, just to find out that the stable reading of the 
>> capacitance meter was
>> 3x off.  A simple test would be to take a 470pF or 1nF capacitor and 
>> measure it with the
>> same instrument.  Alternately, if you have a TDR instrument on hand, 
>> stick it into the
>> planes and record the risetime after the sharp fall caused by the plane 
>> capacitance.
>> The time constant of the rise is 50 Ohms times the (unknown) capacitance.
>>
>> Regards,
>>
>> Istvan Novak
>> Oracle
>>
>>
>> On 9/9/2010 4:14 PM, Mikhail Matusov wrote:
>>> Steve,
>>>
>>> I dug out the manufacturer's report (the card is a few years old). The
>>> dielectric was supposed to be prepreg 3.9 mil thick with Dk of 4.31. The
>>> material was supposedly PCLFR370HR. Although, it seems that we had moved 
>>> a
>>> couple of layers around last minute, so this might be not the latest
>>> report...
>>>
>>>
>>> /Mikhail
>>>
>>>
>>>
>>> ----- Original Message -----
>>> From: "steve weir"<weirsi@xxxxxxxxxx>
>>> To: "Mikhail Matusov"<matusov@xxxxxxxxxxxx>
>>> Cc:<wolfgang.maichen@xxxxxxxxxxxx>;<si-list@xxxxxxxxxxxxx>
>>> Sent: Thursday, September 09, 2010 3:29 PM
>>> Subject: [SI-LIST] Re: Basic question on power plane capacitance
>>>
>>>
>>>> If there isn't much copper connected together on the outer layer, the
>>>> difference is likely that what you think is 5mil dielectric is more 
>>>> like
>>>> 3mil and is almost all glass.  I am a bit surprised because the PWR1 /
>>>> GND1, and GND4 / PWR2 layers s/b core making them well controlled.
>>>>
>>>> Steve.
>>>> Mikhail Matusov wrote:
>>>>> Steve,
>>>>>
>>>>> The stackup is 14-layer, 63 mil thickness:
>>>>>
>>>>> Top
>>>>> PWR1
>>>>> GND1
>>>>> signal1
>>>>> signal2
>>>>> GND2
>>>>> signal3
>>>>> signal4
>>>>> GND3
>>>>> signal5
>>>>> signal6
>>>>> GND4
>>>>> PWR2
>>>>> Bottom
>>>>>
>>>>> Some of the GND planes actually contain polygons with other voltages.
>>>>>
>>>>> The actual polygon in question is not a simple rectangle, it kind of
>>>>> looks
>>>>> like the letter F.
>>>>>
>>>>> /Mikhail
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> ----- Original Message -----
>>>>> From: "steve weir"<weirsi@xxxxxxxxxx>
>>>>> To: "Mikhail Matusov"<matusov@xxxxxxxxxxxx>
>>>>> Cc:<wolfgang.maichen@xxxxxxxxxxxx>;<si-list@xxxxxxxxxxxxx>
>>>>> Sent: Thursday, September 09, 2010 2:47 PM
>>>>> Subject: [SI-LIST] Re: Basic question on power plane capacitance
>>>>>
>>>>>
>>>>>
>>>>>> Mikhail, your dimensions sound like 13.5mm x 104.5mm give or take. 
>>>>>> That
>>>>>> is still more than 100X your height on the short axis.  So I do not
>>>>>> suspect fringing.  What is your actual stack-up?
>>>>>>
>>>>>> Steve
>>>>>>
>>>>>>
>>>>>>
>>>>>> Mikhail Matusov wrote:
>>>>>>
>>>>>>> Thanks Wolfgang and all,
>>>>>>> Yes, indeed I haven't thought of fringe capacitance. I don't know if
>>>>>>> there is an easy analytical way to find out what it will be. The 
>>>>>>> area
>>>>>>> of
>>>>>>> the polygon is 1400 sq.mm. The perimeter is 236 mm. The dielectric 
>>>>>>> is
>>>>>>> FR-4, and the thikness is about 5 mil (0.127mm). The top layer is 
>>>>>>> not a
>>>>>>> plane and there is not much copper in it, mostly pads and vias. The 
>>>>>>> gap
>>>>>>> around this polygon separating it from the rest of the plane is 15 
>>>>>>> mil
>>>>>>> (0.381mm) wide. The board dimensions are 233x160 mm.
>>>>>>>
>>>>>>> Thanks again,
>>>>>>> /Mikhail
>>>>>>>
>>>>>>>
>>>>>>>    ----- Original Message -----
>>>>>>>    From: wolfgang.maichen@xxxxxxxxxxxx
>>>>>>>    To: Mikhail Matusov
>>>>>>>    Cc: si-list@xxxxxxxxxxxxx ; si-list-bounce@xxxxxxxxxxxxx
>>>>>>>    Sent: Thursday, September 09, 2010 2:11 PM
>>>>>>>    Subject: Re: [SI-LIST] Basic question on power plane capacitance
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>    Mikhail,
>>>>>>>
>>>>>>>    If the polygon isn't very large (~100x) compared to its distance 
>>>>>>> from
>>>>>>> the ground plane then fringe capacitance will contribute 
>>>>>>> significantly
>>>>>>> to
>>>>>>> the total value - i.e. the actual capacitance will be quite a bit
>>>>>>> higher
>>>>>>> than what you'd expect from the simple formula for a planar 
>>>>>>> capacitor.
>>>>>>> In
>>>>>>> addition, if your dielectric is a low-cost material (e.g. FR-4) its
>>>>>>> dielctric constant can easily be off by ~10% from the specified 
>>>>>>> value.
>>>>>>>
>>>>>>>    A 2.5D or 3D field solver can tell you how much total capacitance 
>>>>>>> to
>>>>>>> expect. One suitable choice would be Sonnet Lite (i.e. the demo 
>>>>>>> version
>>>>>>> of Sonnet). If you can tell me the size/geometry of your polygon,
>>>>>>> distance to the ground plane, and dielectric constant of the board
>>>>>>> material I can run a quick simulation for you.
>>>>>>>
>>>>>>>    Just to rule out an obvious mistakes, you did take into account 
>>>>>>> that
>>>>>>> having both a plane below and above the polygon will douple the
>>>>>>> capacitance compared to just a single pair (polygon and single 
>>>>>>> ground
>>>>>>> plane)? Forgetting that would immediately explain a mismatch factor 
>>>>>>> of
>>>>>>> 2.
>>>>>>>
>>>>>>>    Regards,
>>>>>>>
>>>>>>>    Wolfgang
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>          "Mikhail Matusov"<matusov@xxxxxxxxxxxx>
>>>>>>>          Sent by: si-list-bounce@xxxxxxxxxxxxx
>>>>>>>          09/09/2010 10:50 AM
>>>>>>>         To<si-list@xxxxxxxxxxxxx>
>>>>>>>                cc
>>>>>>>                Subject [SI-LIST] Basic question on power plane
>>>>>>> capacitance
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>    Hi all,
>>>>>>>
>>>>>>>    I have a small polygon in a plane layer of a multi-layer PCB. 
>>>>>>> There
>>>>>>> is
>>>>>>> a
>>>>>>>    solid ground plane underneath it and the top signal layer above. 
>>>>>>> I
>>>>>>> have
>>>>>>>    calculated from the basic plane capacitance equation that the 
>>>>>>> plane
>>>>>>>    capacitance for this polygon should be in the range of 420 pF.
>>>>>>> However,
>>>>>>> I am
>>>>>>>    measuring 890 pF with one meter and 1 nF with another. I was
>>>>>>> wondering
>>>>>>> what
>>>>>>>    am I doing wrong?
>>>>>>>
>>>>>>>
>>>>>>>    Thanks,
>>>>>>>    /Mikhail
>>>>>>>
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>>>>>> -- 
>>>>>> Steve Weir
>>>>>> IPBLOX, LLC
>>>>>> 150 N. Center St. #211
>>>>>> Reno, NV  89501
>>>>>> www.ipblox.com
>>>>>>
>>>>>> (775) 299-4236 Business
>>>>>> (866) 675-4630 Toll-free
>>>>>> (707) 780-1951 Fax
>>>>>>
>>>>>>
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>>>>>>
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>>>> -- 
>>>> Steve Weir
>>>> IPBLOX, LLC
>>>> 150 N. Center St. #211
>>>> Reno, NV  89501
>>>> www.ipblox.com
>>>>
>>>> (775) 299-4236 Business
>>>> (866) 675-4630 Toll-free
>>>> (707) 780-1951 Fax
>>>>
>>>>
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