[SI-LIST] Back of the envelope termination resistor calculation
- From: Alex Horvath <alexh1@xxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 8 Dec 2005 16:27:13 -0800 (PST)
Hi,
In the past when trying to determine if a series term resistor is required or
what the value should be I would use the IBIS file to determine the approximate
output resistance of the gate. Also it could be used to determine if incident
wave switching is possible which can often be a make or break situation. I
think I read about this technique in Halls book but I'm not sure. I presently
have occasion to do that and although I know this is a crude approximation I
wanted to make sure that I was doing it correctly.
I'm referring to run of the mill LVTTL outputs here.
From the IBIS I determined the following from the Pulldown curve (taking
voltage and dividing by typ current) -
0.5V - 25 Ohms
1.0V - 29 Ohms
1.5V - 35 Ohms
2.0V - 45 Ohms
The thing that disturbs me here is that the non-linearity is much higher than
I would have expected so perhaps this method should be applied with extreme
caution.
I find it amazing that I still end up working with experienced engineers that
have little concept of signal integrity or timing verification (hence the
unavailability of an SI tool at my current employer). In my case my first job
out of college was designing avionics. Obviously avionics must be completely
reliable and we had a rule that all interchip paths had to have a 20% timing
margin so the importance of "correct by design" was instilled in me early in my
career.
Of course in those days edge rates were relatively slow so most paths could
be treated as lumped and if not the ridiculously high drive current of the
jellybean logic of that time allowed us to use parallel terminations. Thus the
20% margin rule was easy to apply from the device data sheets in most cases.
Thanks
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