[SI-LIST] Re: BGA vias outside the package

Under your circumstances, there does not seem to be any other option. For 180 
MHz, the part should work. Few things that come to my mind

1. The larger via will not help much. It does provide some capacitance but it 
will not help the inductance of the trace connecting the via to the BGA.

2. You may try to keep the power and ground traces close by ( either in top 
layer or in the form of adjacent gnd layer or by routing them close by in top 
layer). This should not slightly help in very high frequency noise.

3. Identify power pins not internally short. Route them slightly away.

4. I did some design using via in pad. The via went from top layer to layer2 ( 
ground) and top layer to layer3 (power). In my case I was able to get a 8 layer 
board for about $25 each for 100 boards. So I will say that you may still like 
to explore it.

Vikas Shukla 


--- On Wed, 1/28/09, Ryan Sequeira <ryan.sequeira@xxxxxxxxxx> wrote:

> From: Ryan Sequeira <ryan.sequeira@xxxxxxxxxx>
> Subject: [SI-LIST] BGA vias  outside the package
> To: si-list@xxxxxxxxxxxxx
> Date: Wednesday, January 28, 2009, 5:20 AM
> Would like to understand the effects of supplying power and
> ground to the
> BGA by connecting
> vias to the VCC/GND plains and traces outside the BGA
> package. 
> 
> Pros: Allows for larger vias outside the package.
> Cons: Compromised noise performance through trace length
> added to VCC/GND
> trace length.
> 
> Is there something else that needs to be taken care of....
> 
> The BGA device is a CPLD, IO=3.3V, Core=1.8V, Fmax =
> 180MHz, VCCO(3.3V) - 11
> pins, VCC(1.8V) - 4 pins, GND - 15 pins
> The device is a 132csBGA, 0.5mm pitch, 0.3mm pad. So cannot
> afford to drop
> the vias within the BGA area. Microvias would be too
> expensive...
> 
> Ryan
> 
> 
> 
> 
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