[SI-LIST] Re: BGA vias outside the package

Hello Ryan,
using thin traces to supply any significant amount of supply current is 
usually not a good idea. The main enemy for power supply stability is 
inductance, not resistance.

While the thicker via won't buy you much in terms of reeduced impedance, 
the trace will greatly increase the loop inductance. So in total your loop 
inductance will go up by a factor of probably 5 - 10. A transmission line 
calculator or a 2D field solver can give more precise numbers as to the 
inductance of a piece of trace. Compare that to ~1nH (order of magnitude) 
for a direct via connection.

Since routing space under a large BGA is very constricted, I highly 
recommend using filled vias (also called via-in-pad), and to connect ALL 
power and GND balls directly with a via to the respective power and ground 
plane(s). This will give you the lowest supply inductance and at the same 
time maximize your routing space. Not using traces for power supply also 
means you free up space that can then be used to route signals - possibly 
reducing the required number of layers in the stackup, which can 
compensate for the additional cost of the filled vias. Another good trick 
is to place the smallest value decoupling capacitors on the other side of 
the board, right below the BGA. With via in pad and 1mm ball grid the 
typical 100nF 0402 package size capacitors fit perfectly onto the grid.

Hope that gives you a few ideas. 

Wolfgang





"Ryan Sequeira" <ryan.sequeira@xxxxxxxxxx> 
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01/28/2009 03:20 AM

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[SI-LIST] BGA vias  outside the package






Would like to understand the effects of supplying power and ground to the
BGA by connecting
vias to the VCC/GND plains and traces outside the BGA package. 

Pros: Allows for larger vias outside the package.
Cons: Compromised noise performance through trace length added to VCC/GND
trace length.

Is there something else that needs to be taken care of....

The BGA device is a CPLD, IO=3.3V, Core=1.8V, Fmax = 180MHz, VCCO(3.3V) - 
11
pins, VCC(1.8V) - 4 pins, GND - 15 pins
The device is a 132csBGA, 0.5mm pitch, 0.3mm pad. So cannot afford to drop
the vias within the BGA area. Microvias would be too expensive...

Ryan




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