[SI-LIST] Re: BGA design considerations?
- From: "Brad Brim" <bradb@xxxxxxxxxxx>
- To: "'Mike Sims'" <mike.simsusa@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Sat, 28 May 2011 14:44:08 -0700
hi Mike, There are constraint-driven physical design (i.e. layout) tools for BGA packages. In fact, there are now even tools for BGA packages that will perform auto routing. Such EDA tools support both physical and electrical constraints. Physical constraints might be things like spacings, widths, individual or diff-pair trace lengths, etc. Electrical constraints might be things like parasitic values, impedance or crosstalk. Of course, these physical design tools typically only approximate such electrical parasitics and you will need to perform a package "extraction" to determine reliable parasitic values. There are a number of extraction tools available for BGA packages and some are linked well with constraint-driven layout tools. You can extract RLCK IBIS/SPICE models or you can extract S-parameter models, depending on the electrical size of your power domains and your signal nets. If you apply human generated approximate models (traces, vias, balls/bumps individual models concatenated together in an equivalent circuit) you are relying on a zeroth-order approximation that completely ignore power delivery. Few SI/PI analysts and systems engineers find such models adequate. The RLCK models can be per-net or per-pin resolution. I have extracted per-pin resolution models for packages with literally several thousand pins between power and signals. Broadband and S-parameter models tend to be for specific buses in the package, including both signals and local power, and not necessarily the whole package. Power delivery analysis often includes the entire core or IO power domains with per-pin resolution. The objective of power delivery is typically higher level than to simply generate a per-pin SPICE model of the entire power deliver network (PDN). In such case you can perform a per-pin "assessment" of the PDN from either die-side or board-side to identify individually weak pin or regions of weak bumps/balls susceptible to high PDN noise. If you are supporting chip-centric chip/package codesign of the PDN with your models you can should be able to get by with per-pin or even pin-grouped RLCK models at the die-side to surprisingly high frequency. You often need only per-net resolution at the board-side in such applications for performing chip-centric analysis. Analogously the reverse is often true for board-centric PDN board/package/chip codesign: per-pin or grouped-pin board-side RLCK models with per-net die-side resolution and lumped RC chip PDN model. When you move to SI analysis you will likely need more resolution in your models and high-speed IOs may well require more bandwidth than an RLCK package model can support. Package extraction tools have classically been intended to support IBIS/SPICE model generation only. More recently these EDA tools support PDN per-pin "assessment" for R and L parasitics, checking of signal trace impedance/coupling; as well as a ton of postprocessing of model data for things such as per-net parasitics, parasitics plotted versus net length, crosstalk values, etc. You can compare these plots from one design version to the next to support predictive design refinements for fully-informed decision making - for example, is it worth the cost of going from a 6-layer implementation to an 8-layer for the reductions you see in electrical parasitics? good luck with your new pursuits in BGA package design, -Brad Brim Sigrity > -----Original Message----- > From: si-list-bounce@xxxxxxxxxxxxx > [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Mike Sims > Sent: Saturday, May 28, 2011 1:21 PM > To: si-list@xxxxxxxxxxxxx > Subject: [SI-LIST] BGA design considerations? > > Hello All, > I am new to this so trying to learn :) > > I am just wondering what are the design considerations when > designing a BGA layout? Obviously the location of signals and > where they need to come out is important but beyond that what > about parasitics and stuff like that? > placements of gnd/pwr balls relative to signals? > > I have seen the BGA design in excel files in past. Is there a > tool for simulating the parasitics of the balls? How is > impact of moving a ball to a new location simulated? Is there > an iterative way to figure out the best possible location of > a ball (with some restrictions like the ball must be between > A5 and C8, etc. or diff pairs must remain together, etc)? > > Thanks for your help. > > Mike Sims > > > ------------------------------------------------------------------ > To unsubscribe from si-list: > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field > > or to administer your membership from a web page, go to: > http://www.freelists.org/webpage/si-list > > For help: > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field > > > List technical documents are available at: > http://www.si-list.net > > List archives are viewable at: > http://www.freelists.org/archives/si-list > > Old (prior to June 6, 2001) list archives are viewable at: > http://www.qsl.net/wb6tpu > > > ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: http://www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: http://www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu
- [SI-LIST] BGA design considerations?
- From: Mike Sims
- [SI-LIST] BGA design considerations?