[SI-LIST] Re: BGA Breakout.

  • From: steve weir <weirsi@xxxxxxxxxx>
  • To: leeritchey@xxxxxxxxxxxxx
  • Date: Fri, 22 Jan 2010 14:20:22 -0800

Lee, there are multiple manufacturers of thin dielectric I do work for 
one of them.  Thin dielectric is a tool like anything else.  If used 
properly it is an advantage.

Best Regards,


Steve.
Lee Ritchey wrote:
> Steve,
>
> Looks like you still have your sales hat on!
>
>
>   
>> [Original Message]
>> From: steve weir <weirsi@xxxxxxxxxx>
>> To: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
>> Cc: Istvan Novak <istvan.novak@xxxxxxx>; Sol Tatlow
>>     
> <Sol.Tatlow@xxxxxxxxxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>; Surita Chandani
> <surita.chandani@xxxxxxxxx>
>   
>> Date: 1/21/2010 2:36:24 PM
>> Subject: [SI-LIST] Re: BGA Breakout.
>>
>> Lee that is just the sort of situation where thin dielectric could make 
>> your life much easier.
>>
>> 1. With thin dielectric you can hit impedance targets with polygons that 
>> form a much smaller included angle than with thicker dielectric.  This 
>> allows you to combine more PDN rails on a given power layer and reduce 
>> layer count.
>>
>> 2. Thin dielectric cuts the overall PCB thickness.  This reduces the 
>> aspect ratio of the drills and improves PCB yield which can save a huge 
>> amount of money.
>>
>> Best Regards,
>>
>>
>> Steve.
>> Lee Ritchey wrote:
>>     
>>> Isvan,
>>>
>>> Well put.
>>>
>>> Lately, I find layer needs driven by PDN requirements in many systems. 
>>>       
> One
>   
>>> recent design had 17 different PDN zones requiring 6 plane pairs just
>>>       
> for
>   
>>> power.  A couple of 2000 pin parts drove the wire need to 12 signal
>>>       
> layers,
>   
>>> resulting in a fairly thick PCB, even when using thin cores.  This drove
>>> the drill size for plating purposes, so that only one trace fit betwen
>>>       
> pins.
>   
>>> As you noted, what you can do depends on what you have to package and
>>>       
> the
>   
>>> reliability standards that must be complied with.
>>>
>>> Lee
>>>
>>>
>>>   
>>>       
>>>> [Original Message]
>>>> From: Istvan Novak <istvan.novak@xxxxxxx>
>>>> To: Sol Tatlow <Sol.Tatlow@xxxxxxxxxxxxxxxxxxxx>;
>>>>     
>>>>         
>>> <leeritchey@xxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
>>>   
>>>       
>>>> Cc: Surita Chandani <surita.chandani@xxxxxxxxx>
>>>> Date: 1/21/2010 6:10:50 AM
>>>> Subject: [SI-LIST] Re: BGA Breakout.
>>>>
>>>> Sol, Lee and All,
>>>>
>>>> In addition to the excellent explanations and summaries of options,
>>>>         
> let 
>   
>>>> me offer a couple of more
>>>> considerations that could go into such a decision.
>>>>
>>>> 1) The number of traces between vias create a sort of positive
>>>>         
> feedback 
>   
>>>> with some hysteresis in the
>>>> early stages of stackup selection.  Since (short of asymmetrical 
>>>> patterns creating alternating widths
>>>> of routing channels) we are down to very small numbers, either one or 
>>>> two, assuming either of the
>>>> two cases has significant consequences on the overall board thickness, 
>>>> hence the positive feedback.
>>>> If we decide to escape one in between, it will drive up layer count, 
>>>> increase board thickness, which
>>>> may require us to go to the next bigger via size with bigger antipads, 
>>>> which further limits the
>>>> width of available routing channels.  If we wanted to escape two
>>>>         
> traces 
>   
>>>> between vias, it will lower
>>>> the necessary layer count, so we can afford smaller via drill size, 
>>>> which comes with smaller antipads,
>>>> which opens up the width of routing channels.  When we factor in all
>>>>         
> of 
>   
>>>> the other parameters and
>>>> considerations already mentioned, we usually end up with a solution 
>>>> space, which can be done
>>>> either way, both options can be made to work reliably, but both will
>>>>         
> be 
>   
>>>> close to its limit.  The
>>>> hysteresis in this decision process comes from the fact that we have
>>>>         
> to 
>   
>>>> deal with very small integer
>>>> numbers, so the quantization change is big.
>>>>
>>>> 2) The above overlapping regions of solution spaces get modulated by
>>>>         
> the 
>   
>>>> extra thickness in the
>>>> stackup that we have to set aside for power distribution.  The 
>>>> partitioning of the system and the
>>>> PDN requirements of the devices going onto the board may make a big 
>>>> difference.  Since we cant
>>>> switch the stackup  definition over the board area dependent on local 
>>>> needs, the number of power
>>>> layers and weight of copper will be dictated by the most stringent
>>>>         
> local 
>   
>>>> requirement on the board.
>>>> Some high-power boards may require more than half of the stackup
>>>>         
> height 
>   
>>>> going to power distribution.
>>>> We may not need all of the copper weight and all of the layers under
>>>>         
> any 
>   
>>>> particular high pin-count chip
>>>> (though many times we do), the overall stackup will need to be taller 
>>>> just because somewhere else
>>>> on the board we need it.  The PDN requirements of the chips can help
>>>>         
> or 
>   
>>>> hurt a lot, too.  The
>>>> number of independent power domains on the chip will eventually 
>>>> determine how many power
>>>> layers we need to feed the chip.  More independent domains (unless 
>>>> horizontally well separated) usually
>>>> means more power planes, hence taller stackup, stressing the via
>>>>         
> aspect 
>   
>>>> ratio and narrowing available
>>>> routing channels.
>>>>
>>>> Regards,
>>>>
>>>> Istvan Novak
>>>> SUN Microsystems
>>>>
>>>> Sol Tatlow wrote:
>>>>     
>>>>         
>>>>> Lee,
>>>>> When I decided in 2001/2002 to go for 2 traces between 1mm pitch
>>>>>           
> vias, I
>   
>>>>> did so on the basis of 10 years layouting experience, detailed
>>>>>           
> knowledge
>   
>>>>> of the PCB manufacturing process, and close contact with a small
>>>>>           
> handful
>   
>>>>> of high quality PCB manufacturers - I like to be at least 99% sure
>>>>>           
> that
>   
>>>>> I'm doing the right thing before I do it... although I recognise, even
>>>>> if I'm 100% sure I'm right, I'm still wrong sometimes (particularly in
>>>>> 'discussions' with my better-half :)!).
>>>>>
>>>>> Nevertheless, thanks for the article - nicely written, containing much
>>>>> of the basic PCB manufacturing information that I find many
>>>>> layouters/engineers _should_ be fully aware of, but aren't. Actually,
>>>>>           
> it
>   
>>>>> astounds me how few people seem to even begin to use such resources
>>>>>           
> that
>   
>>>>> so many well-educated and/or well-informed professionals like yourself
>>>>> go to the effort to make freely available - a few minutes to google
>>>>>           
> and
>   
>>>>> the motivation to self-educate are all they really need.
>>>>>
>>>>> Anyway, I think where we are kind of getting short-circuited :) has
>>>>> simply (or at least mostly) to do with the board thickness: based on
>>>>> your assumption of 120 mil boards, I would essentially agree with
>>>>> everything in your article. What I _wouldn't_ agree with is that a
>>>>>           
> 1400+
>   
>>>>> ball BGA necessarily (or even usually) requires 22-26+ layers, and
>>>>> therefore a 100+ mil board, and therefore only one trace between vias
>>>>> would be possible; that there are board thicknesses where 2 traces
>>>>> between 1mm pitch vias makes no sense, or is physically impossible,
>>>>> should be clear and was never an issue for me.
>>>>>
>>>>> As I wrote, I take measures to make sure that I don't even approach
>>>>>           
> this
>   
>>>>> thickness (where possible), exactly _because_ of the reasons you
>>>>> mentioned. At around 20 layers/2,0mm board thickness (even up to 26
>>>>> layers/2,4mm), the problems are the same... BUT the numbers are
>>>>> different: a 0,2mm (8 mil) or 0,25mm (10 mil) drill is then (depending
>>>>> upon exact board thickness and manufacturer) no problem with regards
>>>>>           
> to
>   
>>>>> achieving adequate plating in the vias. This, as I said, opens the way
>>>>> to 0,5mm (20 mil) via pads and 2 traces between the via with no risk
>>>>>           
> of
>   
>>>>> bad yields (provided good layouting techniques are employed, of
>>>>> course!), leading in turn to more affordable boards.
>>>>>
>>>>> That this may mean you have to consider differential pair
>>>>> coupling/routing at a different level than just whether you can
>>>>>           
> achieve
>   
>>>>> a required impedance or not, is (or should be) a no-brainer, hence the
>>>>> simple and short comment in the first paragraph of my last mail (that
>>>>>           
> it
>   
>>>>> depends upon how the signals are to be routed). At the end of the day,
>>>>> not all high-ballcount BGAs require all signal pins to be routed
>>>>> differentially for 10+ GHz :).
>>>>>
>>>>> Another possibly critical factor is the targeted production volume,
>>>>>           
> for
>   
>>>>> obvious reasons - with regards to that, you don't specify a number in
>>>>> your article and I didn't mention this in my first email. Really,
>>>>>           
> it's a
>   
>>>>> key question that has to be asked right at the beginning of any
>>>>>           
> project,
>   
>>>>> as I'm sure you know and appreciate - I think we both failed to ask
>>>>>           
> this
>   
>>>>> key question before volunteering an answer, or rather, we should have
>>>>> mentioned it as a qualifying factor.
>>>>>
>>>>> Still, there are many other factors that could be discussed too, but
>>>>>           
> the
>   
>>>>> basic essence of my answer was and remains: I am 100% sure that it
>>>>>           
> could
>   
>>>>> (perhaps even should) easily be possible for Surita to produce a
>>>>> functioning and reliable volume-production layout for a 1400+ ball BGA
>>>>> running 2 traces between 1mm pitch vias, just as the original Intel
>>>>> application note states. My personal experience confirms this, at
>>>>>           
> least
>   
>>>>> for me.
>>>>>
>>>>> Although... maybe this is one of those cases where I am 100% sure I'm
>>>>> right, but I'm still wrong ;)?!
>>>>>
>>>>> Regards,
>>>>> Sol
>>>>>
>>>>> P.S. Before 2001, I also, as Robert Szumowicz mentioned, resorted to
>>>>> off-grid vias for some years, back in the days when most people quaked
>>>>> in their boots at the idea of 0,1mm and smaller traces... actually, I
>>>>> thought _I_ had "invented" it - damn ;)!
>>>>>
>>>>>
>>>>>
>>>>> Lee Ritchey schrieb:
>>>>>   
>>>>>       
>>>>>           
>>>>>> Sol,
>>>>>>
>>>>>> I have attached an analysis I did of clearances, tolerances and
>>>>>>         
>>>>>>             
>>> reliability
>>>   
>>>       
>>>>>> requirements when routing PCBs.  Hope this makes it clear what the
>>>>>>         
>>>>>>             
>>> risks
>>>   
>>>       
>>>>>> are when routing 2 between on 1 mm pitch BGAs.
>>>>>>
>>>>>> Lee
>>>>>>
>>>>>>
>>>>>>   
>>>>>>     
>>>>>>         
>>>>>>             
>>>>>>> [Original Message]
>>>>>>> From: Sol Tatlow <Sol.Tatlow@xxxxxxxxxxxxxxxxxxxx>
>>>>>>> To: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
>>>>>>> Cc: Surita Chandani <surita.chandani@xxxxxxxxx>;
>>>>>>>           
>>>>>>>               
>>> <si-list@xxxxxxxxxxxxx>
>>>   
>>>       
>>>>>>> Date: 1/18/2010 1:39:42 PM
>>>>>>> Subject: [SI-LIST] Re: BGA Breakout.
>>>>>>>
>>>>>>> With all respect, Lee, I beg to differ (at least a little bit ;)!):
>>>>>>>               
> I
>   
>>>>>>> personally have routed many boards with 1mm BGAs of over 1700 balls
>>>>>>> (with 1200+ signals, ALL 1700+ balls connected), and, depending upon
>>>>>>>           
>>>>>>>               
>>> how
>>>   
>>>       
>>>>>>> these signals are to be routed (which is, admittedly, a fairly big
>>>>>>> 'depending'), 18 layers can be (and usually is) enough already.
>>>>>>> Since roughly 2001/2002, I have had such BGAs on boards where I
>>>>>>> generally have around 18-20 layers in <2,0mm (78 mil) together with
>>>>>>> 0,5mm (20mil) via pads (the drill doesn't really interest me, in
>>>>>>> general, just the reliability of the results!) - this leaves 0,1mm
>>>>>>>               
> (4
>   
>>>>>>> mil) track and gap (roughly speaking) for 2 tracks between vias...
>>>>>>>               
> and
>   
>>>>>>> the '2 traces between the vias' is the key to holding down board
>>>>>>> thickness and layer count. This has worked for me even up to 26
>>>>>>>               
> layers
>   
>>>>>>> and ~2,5mm board thickness.
>>>>>>>
>>>>>>> With (in the meantime) 30,000-60,000 component pins/balls per board,
>>>>>>>           
>>>>>>>               
>>> and
>>>   
>>>       
>>>>>>> a resulting via count of only somewhat less than the pin count, it
>>>>>>>               
> is
>   
>>>>>>> still possible to have these boards manufactured in series
>>>>>>>               
> quantities
>   
>>>>>>>           
>>>>>>>               
>>> at
>>>   
>>>       
>>>>>>> affordable prices from a comfortable number of manufacturers around
>>>>>>>           
>>>>>>>               
>>> the
>>>   
>>>       
>>>>>>> world; the results, in some cases, have been in operation since 2002
>>>>>>>           
>>>>>>>               
>>> and
>>>   
>>>       
>>>>>>> we have very good reliability results across the board (I sweated
>>>>>>>               
> back
>   
>>>>>>> then a little, but in the meantime, it's 100% normal... I sleep
>>>>>>>               
> easily
>   
>>>>>>> at night now :D!!).
>>>>>>>
>>>>>>> One typical problem occurs, of course, in the planning phase: if you
>>>>>>> assume too many power/gnd _pairs_ (as opposed to _individual_ gnd or
>>>>>>>           
>>>>>>>               
>>> pwr
>>>   
>>>       
>>>>>>> layers), you are automatically forced to have a thicker board, where
>>>>>>>           
>>>>>>>               
>>> it
>>>   
>>>       
>>>>>>> may no longer be possible to have small enough vias to route 2
>>>>>>>               
> tracks
>   
>>>>>>> between the vias; this is a downward spiral, of course, forcing the
>>>>>>> number of signal layers up, and then again, the pwr/gnd count.
>>>>>>>
>>>>>>> I have, up until now, avoided having exclusively pwr/gnd power
>>>>>>> sandwiches (however nice an idea these are) for exactly this reason;
>>>>>>> instead, alternating (in general) GND-SIG-SIG-PWR-SIG-SIG- etc.
>>>>>>>           
>>>>>>>               
>>> coupled
>>>   
>>>       
>>>>>>> with good routing strategies has given me very good results - there
>>>>>>>           
>>>>>>>               
>>> are
>>>   
>>>       
>>>>>>> many proponents for always using pwr/gnd 'sandwich' pairs, but this
>>>>>>>           
>>>>>>>               
>>> is,
>>>   
>>>       
>>>>>>> quite simply, not always necessary).
>>>>>>>
>>>>>>> Not that I want to start a fight, Lee, just wanted to voice my
>>>>>>> experience/opinion :D!!
>>>>>>>
>>>>>>> Regards,
>>>>>>> Sol
>>>>>>>
>>>>>>> P.S. What 'affordable' means, depends, of course, on the end product
>>>>>>>           
>>>>>>>               
>>> ;),
>>>   
>>>       
>>>>>>> but usually, the 0,1mm track and gap means reduced costs in
>>>>>>>               
> comparison
>   
>>>>>>> to thicker boards with more coarse structures and higher layer
>>>>>>>           
>>>>>>>               
>>> count...
>>>   
>>>       
>>>>>>> in some cases, you might even go to slightly bigger via pads and
>>>>>>>               
> LESS
>   
>>>>>>> than 0,1mm track and gap, to reduce costs... this depends upon the
>>>>>>> manufacturer, thickness of the board, availability of specific
>>>>>>> materials, etc.
>>>>>>>
>>>>>>> Lee Ritchey schrieb:
>>>>>>>     
>>>>>>>       
>>>>>>>           
>>>>>>>               
>>>>>>>> Surita,
>>>>>>>>
>>>>>>>> I believe this kind of routing is possible with very thin PCBs with
>>>>>>>>             
>>>>>>>>                 
>>> very
>>>   
>>>       
>>>>>>>> small holes such as in laptop motherboards.  However, with very
>>>>>>>>                 
> large
>   
>>>>>>>>       
>>>>>>>>         
>>>>>>>>             
>>>>>>>>                 
>>>>>> BGAs
>>>>>>   
>>>>>>     
>>>>>>         
>>>>>>             
>>>>>>>> such as yours, it is unlikely that it w ill route on a thin PCB. 
>>>>>>>>                 
> My
>   
>>>>>>>> experience with BGAs of your size is that a 22-26 layer PCB will be
>>>>>>>>       
>>>>>>>>         
>>>>>>>>             
>>>>>>>>                 
>>>>>> needed
>>>>>>   
>>>>>>     
>>>>>>         
>>>>>>             
>>>>>>>> and that will likely be 100+ mils thick resulting in the need for
>>>>>>>>                 
> 12
>   
>>>>>>>>             
>>>>>>>>                 
>>> mil
>>>   
>>>       
>>>>>>>> drills.
>>>>>>>>
>>>>>>>> Lee
>>>>>>>>
>>>>>>>>
>>>>>>>>   
>>>>>>>>       
>>>>>>>>         
>>>>>>>>             
>>>>>>>>                 
>>>>>>>>> [Original Message]
>>>>>>>>> From: Surita Chandani <surita.chandani@xxxxxxxxx>
>>>>>>>>> To: <si-list@xxxxxxxxxxxxx>
>>>>>>>>> Date: 1/15/2010 11:43:41 AM
>>>>>>>>> Subject: [SI-LIST] Re: BGA Breakout.
>>>>>>>>>
>>>>>>>>> Thanks Lee for your comments. 
>>>>>>>>> The suggestions for two traces between Vias comes directly from
>>>>>>>>>               
>>>>>>>>>                   
>>> Intel
>>>   
>>>       
>>>>>>>>>     
>>>>>>>>>         
>>>>>>>>>           
>>>>>>>>>               
>>>>>>>>>                   
>>>>>>>> document, also this document is from 2002. Their pitch is 1.067 mm.
>>>>>>>>             
>>>>>>>>                 
>>> The
>>>   
>>>       
>>>>>>>> document itself is available at: 
>>>>>>>>   
>>>>>>>>       
>>>>>>>>         
>>>>>>>>             
>>>>>>>>                 
>>>>>>>>> http://download.intel.com/support/processors/xeon/sb/25039702.pdf 
>>>>>>>>> ; Page 43.
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> --- On Fri, 1/15/10, Lee Ritchey <leeritchey@xxxxxxxxxxxxx> wrote:
>>>>>>>>> Surita,
>>>>>>>>>
>>>>>>>>> You are right, you cannot successfully route two traces between
>>>>>>>>>                   
> pins
>   
>>>>>>>>>         
>>>>>>>>>           
>>>>>>>>>               
>>>>>>>>>                   
>>>>>> on a
>>>>>>   
>>>>>>     
>>>>>>         
>>>>>>             
>>>>>>>>>     
>>>>>>>>>         
>>>>>>>>>           
>>>>>>>>>               
>>>>>>>>>                   
>>>>>>>> 1
>>>>>>>>   
>>>>>>>>       
>>>>>>>>         
>>>>>>>>             
>>>>>>>>                 
>>>>>>>>> mm pitch BGA without significant risk of shorts.
>>>>>>>>>
>>>>>>>>> If you drill a 12 mil hole, your antipad does not have to be
>>>>>>>>>                   
> larger
>   
>>>>>>>>>         
>>>>>>>>>           
>>>>>>>>>               
>>>>>>>>>                   
>>>>>> than
>>>>>>   
>>>>>>     
>>>>>>         
>>>>>>             
>>>>>>>>>     
>>>>>>>>>         
>>>>>>>>>           
>>>>>>>>>               
>>>>>>>>>                   
>>>>>>>> 32
>>>>>>>>   
>>>>>>>>       
>>>>>>>>         
>>>>>>>>             
>>>>>>>>                 
>>>>>>>>> mils.  This leaves you with a 7.37 mil web, which works nicely
>>>>>>>>>                   
> for a
>   
>>>>>>>>>     
>>>>>>>>>         
>>>>>>>>>           
>>>>>>>>>               
>>>>>>>>>                   
>>>>>>>> single
>>>>>>>>   
>>>>>>>>       
>>>>>>>>         
>>>>>>>>             
>>>>>>>>                 
>>>>>>>>> trace, but not two traces..  Your surface or signal layer pads can
>>>>>>>>>               
>>>>>>>>>                   
>>> be
>>>   
>>>       
>>>>>>>>>         
>>>>>>>>>           
>>>>>>>>>               
>>>>>>>>>                   
>>>>>> 24
>>>>>>   
>>>>>>     
>>>>>>         
>>>>>>             
>>>>>>>>> mils for 1 mil annular ring and 26 mils for 2 mil annular ring.
>>>>>>>>>
>>>>>>>>> There will only be pads on inner layers where traces connect.
>>>>>>>>>
>>>>>>>>> By the way, what vendor told you to route 2 traces between pins?
>>>>>>>>>
>>>>>>>>> Lee Ritchey
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>     
>>>>>>>>>         
>>>>>>>>>           
>>>>>>>>>               
>>>>>>>>>                   
>>>>>>>>>> [Original Message]
>>>>>>>>>> From: Surita Chandani <surita.chandani@xxxxxxxxx>
>>>>>>>>>> To: <si-list@xxxxxxxxxxxxx>
>>>>>>>>>> Date: 1/14/2010 9:19:08 AM
>>>>>>>>>> Subject: [SI-LIST] BGA Breakout.
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> Hello Gurus;
>>>>>>>>>>
>>>>>>>>>>  
>>>>>>>>>>
>>>>>>>>>> I am doing some preliminary calculations on the breakout of
>>>>>>>>>> a 1,400+  Ball  , BGA. Roughly one half of them are signal
>>>>>>>>>> connections which would need traces running up to them. The
>>>>>>>>>>                     
> vendor
>   
>>>>>>>>>>       
>>>>>>>>>>           
>>>>>>>>>>             
>>>>>>>>>>                 
>>>>>>>>>>                     
>>>>>>>> claims
>>>>>>>>   
>>>>>>>>       
>>>>>>>>         
>>>>>>>>             
>>>>>>>>                 
>>>>>>>>> you
>>>>>>>>>     
>>>>>>>>>         
>>>>>>>>>           
>>>>>>>>>               
>>>>>>>>>                   
>>>>>>>>>> can run two traces between Vias, my calculations are not adding
>>>>>>>>>>                 
>>>>>>>>>>                     
>>> up, I
>>>   
>>>       
>>>>>>>>>>       
>>>>>>>>>>           
>>>>>>>>>>             
>>>>>>>>>>                 
>>>>>>>>>>                     
>>>>>>>>> have a
>>>>>>>>>     
>>>>>>>>>         
>>>>>>>>>           
>>>>>>>>>               
>>>>>>>>>                   
>>>>>>>>>> few questions.
>>>>>>>>>>
>>>>>>>>>>  
>>>>>>>>>>
>>>>>>>>>> 1. Generally, do the Vias have a pad even on the signal
>>>>>>>>>> layer it is not connecting to?.
>>>>>>>>>>
>>>>>>>>>>  
>>>>>>>>>>
>>>>>>>>>> 2. Do the Vias have a larger pad on the inner layers?
>>>>>>>>>>
>>>>>>>>>>  
>>>>>>>>>>
>>>>>>>>>> 3.  With a Ball pitch
>>>>>>>>>> of 1 mm (39 mils.) and an Antipad of 35 mils, there is hardly any
>>>>>>>>>>                 
>>>>>>>>>>                     
>>> room
>>>   
>>>       
>>>>>>>>>>       
>>>>>>>>>>           
>>>>>>>>>>             
>>>>>>>>>>                 
>>>>>>>>>>                     
>>>>>>>>> for one
>>>>>>>>>     
>>>>>>>>>         
>>>>>>>>>           
>>>>>>>>>               
>>>>>>>>>                   
>>>>>>>>>> trace between Vias, what am I doing wrong?
>>>>>>>>>>
>>>>>>>>>>  
>>>>>>>>>>
>>>>>>>>>> Thanks, 
>>>>>>>>>>
>>>>>>>>>>  
>>>>>>>>>>
>>>>>>>>>> Surita Chandani
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>        
>>>>>>>>>>             
>>>>>>>>>>                 
>>>>>>>>>>                     
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