[SI-LIST] Re: BGA Breakout.

Should we ignore the other areas where he has posted opinions? :)

 

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of Scott McMorrow
Sent: Wednesday, January 20, 2010 1:54 PM
To: Lee Ritchey
Cc: Sol Tatlow; Surita Chandani; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: BGA Breakout.

In my opinion, this is one area where everyone should listen to Lee.  
He's been creating successful, highly manufacturable designs for at least a few 
years.


Lee Ritchey wrote:
> Sol,
> I have attached an analysis I did of clearances, tolerances and reliability
> requirements when routing PCBs.  Hope this makes it clear what the risks
> are when routing 2 between on 1 mm pitch BGAs.
>
> Lee
>
>
>   
>> [Original Message]
>> From: Sol Tatlow <Sol.Tatlow@xxxxxxxxxxxxxxxxxxxx>
>> To: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
>> Cc: Surita Chandani <surita.chandani@xxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
>> Date: 1/18/2010 1:39:42 PM
>> Subject: [SI-LIST] Re: BGA Breakout.
>>
>> With all respect, Lee, I beg to differ (at least a little bit ;)!): I
>> personally have routed many boards with 1mm BGAs of over 1700 balls
>> (with 1200+ signals, ALL 1700+ balls connected), and, depending upon how
>> these signals are to be routed (which is, admittedly, a fairly big
>> 'depending'), 18 layers can be (and usually is) enough already.
>> Since roughly 2001/2002, I have had such BGAs on boards where I
>> generally have around 18-20 layers in <2,0mm (78 mil) together with
>> 0,5mm (20mil) via pads (the drill doesn't really interest me, in
>> general, just the reliability of the results!) - this leaves 0,1mm (4
>> mil) track and gap (roughly speaking) for 2 tracks between vias... and
>> the '2 traces between the vias' is the key to holding down board
>> thickness and layer count. This has worked for me even up to 26 layers
>> and ~2,5mm board thickness.
>>
>> With (in the meantime) 30,000-60,000 component pins/balls per board, and
>> a resulting via count of only somewhat less than the pin count, it is
>> still possible to have these boards manufactured in series quantities at
>> affordable prices from a comfortable number of manufacturers around the
>> world; the results, in some cases, have been in operation since 2002 and
>> we have very good reliability results across the board (I sweated back
>> then a little, but in the meantime, it's 100% normal... I sleep easily
>> at night now :D!!).
>>
>> One typical problem occurs, of course, in the planning phase: if you
>> assume too many power/gnd _pairs_ (as opposed to _individual_ gnd or pwr
>> layers), you are automatically forced to have a thicker board, where it
>> may no longer be possible to have small enough vias to route 2 tracks
>> between the vias; this is a downward spiral, of course, forcing the
>> number of signal layers up, and then again, the pwr/gnd count.
>>
>> I have, up until now, avoided having exclusively pwr/gnd power
>> sandwiches (however nice an idea these are) for exactly this reason;
>> instead, alternating (in general) GND-SIG-SIG-PWR-SIG-SIG- etc. coupled
>> with good routing strategies has given me very good results - there are
>> many proponents for always using pwr/gnd 'sandwich' pairs, but this is,
>> quite simply, not always necessary).
>>
>> Not that I want to start a fight, Lee, just wanted to voice my
>> experience/opinion :D!!
>>
>> Regards,
>> Sol
>>
>> P.S. What 'affordable' means, depends, of course, on the end product ;),
>> but usually, the 0,1mm track and gap means reduced costs in comparison
>> to thicker boards with more coarse structures and higher layer count...
>> in some cases, you might even go to slightly bigger via pads and LESS
>> than 0,1mm track and gap, to reduce costs... this depends upon the
>> manufacturer, thickness of the board, availability of specific
>> materials, etc.
>>
>> Lee Ritchey schrieb:
>>     
>>> Surita,
>>>
>>> I believe this kind of routing is possible with very thin PCBs with very
>>> small holes such as in laptop motherboards.  However, with very large
>>>       
> BGAs
>   
>>> such as yours, it is unlikely that it w ill route on a thin PCB.  My
>>> experience with BGAs of your size is that a 22-26 layer PCB will be
>>>       
> needed
>   
>>> and that will likely be 100+ mils thick resulting in the need for 12 mil
>>> drills.
>>>
>>> Lee
>>>
>>>
>>>   
>>>       
>>>> [Original Message]
>>>> From: Surita Chandani <surita.chandani@xxxxxxxxx>
>>>> To: <si-list@xxxxxxxxxxxxx>
>>>> Date: 1/15/2010 11:43:41 AM
>>>> Subject: [SI-LIST] Re: BGA Breakout.
>>>>
>>>> Thanks Lee for your comments. 
>>>> The suggestions for two traces between Vias comes directly from Intel
>>>>     
>>>>         
>>> document, also this document is from 2002. Their pitch is 1.067 mm. The
>>> document itself is available at: 
>>>   
>>>       
>>>> http://download.intel.com/support/processors/xeon/sb/25039702.pdf 
>>>> ; Page 43.
>>>>
>>>>
>>>>
>>>> --- On Fri, 1/15/10, Lee Ritchey <leeritchey@xxxxxxxxxxxxx> wrote:
>>>> Surita,
>>>>
>>>> You are right, you cannot successfully route two traces between pins
>>>>         
> on a
>   
>>>>     
>>>>         
>>> 1
>>>   
>>>       
>>>> mm pitch BGA without significant risk of shorts.
>>>>
>>>> If you drill a 12 mil hole, your antipad does not have to be larger
>>>>         
> than
>   
>>>>     
>>>>         
>>> 32
>>>   
>>>       
>>>> mils.  This leaves you with a 7.37 mil web, which works nicely for a
>>>>     
>>>>         
>>> single
>>>   
>>>       
>>>> trace, but not two traces..  Your surface or signal layer pads can be
>>>>         
> 24
>   
>>>> mils for 1 mil annular ring and 26 mils for 2 mil annular ring.
>>>>
>>>> There will only be pads on inner layers where traces connect.
>>>>
>>>> By the way, what vendor told you to route 2 traces between pins?
>>>>
>>>> Lee Ritchey
>>>>
>>>>
>>>>
>>>>     
>>>>         
>>>>> [Original Message]
>>>>> From: Surita Chandani <surita.chandani@xxxxxxxxx>
>>>>> To: <si-list@xxxxxxxxxxxxx>
>>>>> Date: 1/14/2010 9:19:08 AM
>>>>> Subject: [SI-LIST] BGA Breakout.
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> Hello Gurus;
>>>>>
>>>>>  
>>>>>
>>>>> I am doing some preliminary calculations on the breakout of
>>>>> a 1,400+  Ball  , BGA. Roughly one half of them are signal
>>>>> connections which would need traces running up to them. The vendor
>>>>>       
>>>>>           
>>> claims
>>>   
>>>       
>>>> you
>>>>     
>>>>         
>>>>> can run two traces between Vias, my calculations are not adding up, I
>>>>>       
>>>>>           
>>>> have a
>>>>     
>>>>         
>>>>> few questions.
>>>>>
>>>>>  
>>>>>
>>>>> 1. Generally, do the Vias have a pad even on the signal
>>>>> layer it is not connecting to?.
>>>>>
>>>>>  
>>>>>
>>>>> 2. Do the Vias have a larger pad on the inner layers?
>>>>>
>>>>>  
>>>>>
>>>>> 3.  With a Ball pitch
>>>>> of 1 mm (39 mils.) and an Antipad of 35 mils, there is hardly any room
>>>>>       
>>>>>           
>>>> for one
>>>>     
>>>>         
>>>>> trace between Vias, what am I doing wrong?
>>>>>
>>>>>  
>>>>>
>>>>> Thanks, 
>>>>>
>>>>>  
>>>>>
>>>>> Surita Chandani
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>        
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>> -- 
>> ________________________________________
>>
>> Sol Tatlow, M. Eng. (Oxon)
>> Product Developer
>>
>> Pro Design Electronic GmbH
>> Albert-Mayer-Str. 16
>> D-83052 Bruckmuehl
>> Phone: +49 (0) 8062/808-302
>> PCFax: +49 (0) 8062/808-2302
>> sol.tatlow@xxxxxxxxxxxxxxxxxxxx
>> www.prodesign-europe.com
>> ________________________________________
>>
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>> Helmut Mahr, Ulrike Angersbach, Stephan Roeslmair, Dieter Lessenich
>>
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>>
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>
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-- 
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed(r) is the registered service mark of
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