[SI-LIST] Re: Assymetric stip line

hi

the return current tries to flow in both reference planes, not just in one 
of them.
check this document: 
http://www.buenos.extra.hu/iromanyok/Accurate_Impedance_Control-2columns.pdf
page 7-8, especially the last image on page 7.
also check a previous discussion few days ago on the si-list:  "[SI-LIST] 
Return current and stack up"

regards,
Istvan Nagy,
CCT, UK



----- Original Message ----- 
From: "abin.cv" <abin.cv@xxxxxxxxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>; "rskiruban" <rskiruban@xxxxxxxxxxxxxxxxxx>
Sent: Saturday, June 20, 2009 4:46 AM
Subject: [SI-LIST] Assymetric stip line


> hi,
> Assymetric stip line
>
> Layer 1 GND
> Dielectic 8mils
> Layer 2 Signal (100MHz to 200MHz)
> Dielectric 12mils
> Layer 3 Power (Split plane 3.3V and GND)
>
> The high speed signals (Around 50 signals) in the Layer 2 encounters split 
> in the
> layer 3.  The split width is 10mils. Please let me know whether this split 
> will
> have serious impact on the signal quality.
>
> More over the split plane is 12 mils away from the signal layer.  But the 
> Full GND
> plane (Layer1) is near to the signal.  Won't the signal will take this GND 
> plane as reference
> for their return current.
>
>
> Thanks in advance
>
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