[SI-LIST] Asian IBIS Summit (China) - Agenda

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This message is earlier than normal, but the meeting Agenda
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      Bob Ross, Teraspeed Consulting Group   bob@xxxxxxxxxxxxx
      Lance Wang, IO Methology, Inc.         lwang@xxxxxxxxxx

SIGNUP DEADLINE: September 4, 2007

Bob Ross
Teraspeed Consulting Group

Lance Wang
IO Methodology, Inc.

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        A S I A N   I B I S   S U M M I T    I N F O R M A T I O N

Time/Date:  8:15 - 17:30, Tuesday September 11, 2007

Location:   Park Plaza Hotel Beijing
             25 Zhichum Road
             Haiden District
             Beijing 100083
             CHINA

             Tel:     + 86-10-82356699
             E-mail:  beijing@xxxxxxxxxxxxxxxx

Room:       HongYun Room, 3rd floot
             Check Hotel Meeting Listing

Sponsors:   Huawei Technologies (Primary)
             Agilent Technologies
             Ansoft
             Cadence Design Systems,
             Intel Corporation
             Mentor Graphics Corporation,
             Signal Integrity Software (SiSoft)
             Sigrity
             Synopsys.
             ZTE Corporation

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           I B I S  S U M M I T  M E E T I N G  A G E N D A

8:15    REFRESHMENTS & SIGN IN
           - Vendor Tables Open

9:00    Welcome and Keynote Comments
           - Jiang, XiangZhong
             (Huawei Technologies, China)
           - Mirmak, Michael
             (Chair., EIA IBIS Open Forum, Intel Corporation, USA)
           - Invited Chinese Representative Remarks

9:30    Wang Algebra and Interconnects
           Ross, Bob (Teraspeed Consulting Group, USA)

9:50    IBIS-ATM Update: SerDes Modeling in IBIS
           Westerhoff, Todd (Signal Integrity Software (SiSoft), USA)

10:15   BREAK (Refreshments)

10:30   Serial Link Analysis and PLL Model
           Huang, ChunXing (Huawei Technologies, China)

11:00   A Review of Existing Multi-Gbps Serial Channel Analysis
         Methods and the Evolution of the Proposed ATM Algorithmic
         Modeling Standard
           Dodd, Ian*, Ward, Richard** and Gupta, Sanjeev* (*Agilent
           Technologies, USA and **Texas Instruments, USA)

11:30   An Overview of High-Speed Serial Bus Validation
         Techniques
           Muranyi, Arpad and Dmitriev-Zdorov, Vladimir
           (Mentor Graphics Corporation, USA)

12:00   FREE BUFFET LUNCH (Hosted by Sponsors)
           - Vendor Tables
           - Press Luncheon for IBIS Officers and Sponsors

13:30   Modeling and Simulation for Multi-Gigabit Interconnect
         System
           Zhu, ShunLin, Hu, WeiDong, and Chen, SongRui
           (ZTE Corporation, China)

14:00   Power Deliver System Design Automation
           Xu, Tao (Sigrity, China)

14:30   IBIS 4.2/AMS for DDR2 Timing Analysis
           Guan, Tao (Huawei Technologies, China)

15:00   Validation for IBIS Models
           Wang, Lance*, Zhang, XinJun**, and Yan, Benny**
           (IO Methodology, *USA, **China)

15:25   IBIS Algorithm Including Reactive Loads
           Chen, XueFeng (Synopsys, China)

15:40   BREAK (Refreshments)

15:55   Understanding and Using ICM Models
           Meng, YuBao (Cadence Design Systems, China)

16:25   Using S-Parameters for High Performance Simulation
           Li, BaoLong (Ansoft, China)

16:55   Issues Combining Buffer and Interconnect Model
           Mirmak, Michael (Intel Corporation, USA)

17:15   SerDes Modeling: IBIS-AMI Evaluation Toolkit
           Westerhoff, Todd (Signal Integrity Software (SiSoft), USA)

17:20   IBIS AMI Model Developers Toolbox
           Shah, Hemant (Cadence Design Systems, USA)

17:25   Concluding Items

17:30   END OF IBIS SUMMIT MEETING
           - Final Vendor Tables and Teardown

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-- 
Bob Ross
Teraspeed Consulting Group LLC     Teraspeed Labs
121 North River Drive              13610 SW Harness Lane
Narragansett, RI 02882             Beaverton, OR 97008
401-284-1827                       503-430-1065
http://www.teraspeed.com           503-246-8048 Direct
bob@xxxxxxxxxxxxx

Teraspeed is a registered service mark of Teraspeed Consulting Group LLC

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