[SI-LIST] Re: Article discussion on bad packages

Istvan, thanks.  I should have read your response to Chris more carefully, 
that you are responsible to the PDS, and not signaling.

Regards,


Stve.
At 01:18 PM 12/30/2004 -0500, Istvan NOVAK wrote:
>Steve,
>
>Please note that when I said I do not use SPICE, it was for board-level core
>power distribution.  In that case, you want to make sure that 1) the single
>point of load (the silicon core) is happy, and 2) if the core distribution
>PCB plane is also used as signal reference, the noise on this rail is
>sufficiently low (also for EMI reasons).  In the context of core PDN, SSN
>shows up on the silicon, it affects the PCB only in its cumulative current
>signature, after the current passes through the package 'filter'.
>
>Regards,
>Istvan
>
>
>----- Original Message -----
>From: "steve weir" <weirsp@xxxxxxxxxx>
>To: <istvan.novak@xxxxxxxxxxxxxxxx>; <Chris.Cheng@xxxxxxxxxxxx>
>Cc: <si-list@xxxxxxxxxxxxx>
>Sent: Thursday, December 30, 2004 10:54 AM
>Subject: [SI-LIST] Re: Article discussion on bad packages
>
>
> > Istvan, I am intrigued.  If you haven't been using SPICE, how have you
>been
> > dealing with SSO modeling as it affects your system level design?
> >
> > Regards,
> >
> >
> > Steve.
> > At 10:45 AM 12/30/2004 -0500, Istvan NOVAK wrote:
> > >Chris,
> > >
> > >Re b): since late 1997 I have been designing the PDNs for the
> > >critical boards of the Workgroup Servers, later Volume Servers,
> > >later Horizontal Systems business units (V880, V480, V440 servers,
> > >and newer ones still to be announced).  My primary responsibility
> > >has been board design.  I have also been working closely with
> > >package designers as a board-design stake holder, but ultimatily
> > >package (and silicon) is not my responsibility.
> > >
> > >Re a) for board-level core PDN design, I used to use SPICE.
> > >In recent years, however, I have been using very minimal or none SPICE.
> > >For other business units, and for package/silicon designs: I cant
> > >speak for them.
> > >
> > >Regards,
> > >
> > >Istvan Novak
> > >SUN Microsystems
> > >
> > >----- Original Message -----
> > >From: "Chris Cheng" <Chris.Cheng@xxxxxxxxxxxx>
> > >To: "'Istvan NOVAK '" <istvan.novak@xxxxxxxxxxxxxxxx>; "Chris Cheng"
> > ><Chris.Cheng@xxxxxxxxxxxx>
> > >Cc: <si-list@xxxxxxxxxxxxx>
> > >Sent: Wednesday, December 29, 2004 9:02 PM
> > >Subject: [SI-LIST] Re: Article discussion on bad packages
> > >
> > >
> > > > Istvan,
> > > >
> > > > I would also like to ask the questions for one last time :
> > > > a) Does SUN use IBIS or SPICE to analyze its critical IO or CPU core
>power
> > > > distribution ?
> > > > b) Were you actually responsible to work on the CPU core power
> > >distribution
> > > > analysis for your company ?
> > > > I will be waiting till hell freezes over.
> > > >
> > > > And by the way, m=x is a wonderful marco. It doesn't even have to be
>an
> > > > integer. Comes in handy when the signal to power/ground  ratio is an
>odd
> > > > combination of integers.
> > > >
> > > > -----Original Message-----
> > > > From: Istvan NOVAK
> > > > To: Chris.Cheng@xxxxxxxxxxxx
> > > > Cc: si-list@xxxxxxxxxxxxx
> > > > Sent: 12/29/2004 4:36 PM
> > > > Subject: Re: [SI-LIST] Re: Article discussion on bad packages
> > > >
> > > > Chris,
> > > >
> > > > Let me reiterate my point, which was triggered by your comment
> > > > about the usability of IBIS to SSN problems.  What I wanted
> > > > to say was that dependent on where we are on the
> > > > silicon-package-board design chain, there are situations when
> > > > the full transistor-level model for all the pieces involved may not be
> > > > possible.
> > > >
> > > > Going back to IOs, if we have the transistor-level model for a full IO
> > > > cell,
> > > > we can run SSN simulations on a few cells.  But it becomes impractical
> > > > to use the same level of detail, when we try to figure out the SSN in
> > > > a large package, which may have possibly many hundred IO cells.
> > > > In this case a careful characterization of a single cell should
>provide
> > > > enough information so that a behavioral model can be created to help
> > > > the analysis of the large package.
> > > >
> > > > Regards,
> > > >
> > > > Istvan novak
> > > > SUN Microsystems
> > > >
> > > > ----- Original Message -----
> > > > From: "Chris Cheng" <Chris.Cheng@xxxxxxxxxxxx>
> > > > To: "'Istvan NOVAK '" <istvan.novak@xxxxxxxxxxxxxxxx>; "Chris Cheng"
> > > > <Chris.Cheng@xxxxxxxxxxxx>
> > > > Cc: <si-list@xxxxxxxxxxxxx>
> > > > Sent: Wednesday, December 29, 2004 2:36 PM
> > > > Subject: [SI-LIST] Re: Article discussion on bad packages
> > > >
> > > >
> > > > > Istvan,
> > > > >
> > > > > There is no need to hide behind confidential details, I just asked a
> > > > simple
> > > > > question, does SUN use IBIS to analyze its ""sophisticated IO
> > > > circuits" or
> > > > > core CPU power distribution or does it uses SPICE. It is a simple
>yes
> > > > or
> > > > no
> > > > > answer. And judging from your non-reply, I've got my confirmation.
> > > > > And to answer you question on core power analysis. I would say
> > > > absolutely
> > > > on
> > > > > SPICE. m=x is a very powerful macro, flops and main clock trunk are
> > > > very
> > > > > well defined and hierarchical items. Stages of pipeline and level of
> > > > logics
> > > > > can be estimated on a FUB by FUB basis. Unless your tell me the
>SPARC
> > > > people
> > > > > are using IBIS to analyze their core power. Which I doubt. Were you
> > > > really
> > > > > involved in SUN's chip power analysis with the CPU team ? It doesn't
> > > > sound
> > > > > like it.
> > > > >
> > > > > -----Original Message-----
> > > > > From: Istvan NOVAK
> > > > > To: Chris.Cheng@xxxxxxxxxxxx
> > > > > Cc: si-list@xxxxxxxxxxxxx
> > > > > Sent: 12/29/2004 8:20 AM
> > > > > Subject: Re: [SI-LIST] Re: Article discussion on bad packages
> > > > >
> > > > > Chris,
> > > > >
> > > > > Without going into confidential details, let me answer with a
> > > > > question: do you honestly think that large cores of today's big
> > > > > CPUs can be included at the transistor level for PDN simulations?
> > > > > And even if it was technically possible, do we need all the
> > > > > transistor-level details when we want to simulate the noise at
> > > > > the PCB level?  The package behaves like a redistribution filter,
> > > > > and for the PCB-package interface, all what people need is the
> > > > > distilled characteristics.  It can be IBIS or anything else,
> > > > > eventually it is behavioral model.
> > > > >
> > > > > Regards,
> > > > >
> > > > > Istvan Novak
> > > > > SUN Microsystems
> > > > >
> > > > > ----- Original Message -----
> > > > > From: "Chris Cheng" <Chris.Cheng@xxxxxxxxxxxx>
> > > > > Cc: <si-list@xxxxxxxxxxxxx>
> > > > > Sent: Wednesday, December 29, 2004 12:12 AM
> > > > > Subject: [SI-LIST] Re: Article discussion on bad packages
> > > > >
> > > > >
> > > > > > Istvan,
> > > > > > I thought I understand enough of your company's design
>methodologies
> > > > > (I
> > > > > > worked on quite a few of them). So I am surprised to hear your
> > > > > response.
> > > > > Can
> > > > > > you honest tell me your company is not running SPICE on
> > > > "sophisticated
> > > > > IO
> > > > > > circuits" to analyze its performance nor using it to analyze core
> > > > > power
> > > > > > distribution ? Are you relying only on IBIS nowadays ? Or you are
> > > > > preaching
> > > > > > something you don't practice yourself ?
> > > > > >
> > > > > >
> > > > > > -----Original Message-----
> > > > > > From: Istvan NOVAK
> > > > > > To: Chris.Cheng@xxxxxxxxxxxx
> > > > > > Cc: si-list@xxxxxxxxxxxxx
> > > > > > Sent: 12/28/2004 8:36 PM
> > > > > > Subject: Re: [SI-LIST] Re: Article discussion on bad packages
> > > > > >
> > > > > > Chris,
> > > > > >
> > > > > > If you want to simulate PDN SSN, you can do either a
> > > > > > transistor-level SPICE simulation together with the PDN
> > > > > > model, or an approximate behavioral model simulation can
> > > > > > be done.  For smaller circuits, transistor level models may
> > > > > > work in SPICE (if you have access to it).  For large chunks
> > > > > > of silicon, like CPU cores and sophisticated IO circuits, the
> > > > > > SPICE model may be prohibitively large.  Also, for many
> > > > > > users of third-party silicons, transistor-level SPICE model
> > > > > > may not be available.  For the above reasons, behavioral
> > > > > > simulations may still be better than doing no simulations at all
> > > > > >
> > > > > > Regards,
> > > > > >
> > > > > > Istvan Novak
> > > > > > SUN Microsystems
> > > > > >
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