[SI-LIST] Announcement for the FDIP'03 Workshop





                                    Announcement
       Future Directions in IC and Package Design Workshop, FDIP'03
                               sponsored by:
           IEEE Components, Packaging, and Manufacturing Society

                               organized by:
  CPMT Technical Committee on Electrical Design, Modeling, and Simulation
                                  (TC-12)
                             October 26, 2003
                             Westin Princeton
=09=09=09   Princeton, New Jersey
The goal of this workshop is to provide a forum to address the future needs
associated with the design of next generation ICs and packages.  The
Technical  Program  Committee  will solicit invited presentations from
experts in the university and industrial communities.  The workshop will be
held in conjunction with the IEEE Topical Meeting on Electrical Performance
of Electronic Packaging in order to enhance this conference with
presentations  that  give  directions  for  future  requirements  and
developments in the area of electrical analysis and design.  The workshop
will  foster active participation and discussions from all the speakers and
attendees during the meeting.

                             Workshop Chairs:
Alina Deutsch =09=09IBM Watson Research Center                             =
                       =20
Madhavan Swaminathan=09Georgia Institute of Technology

                       Technical Program Committee:
Tawfik Arabi =E2=80=93 Intel Oregon
Mahadevan Iyer - IME, Singapore
Andreas Cangellaris - University of Illinois
George Katopis - IBM Poughkeepsie
Moises Cases - IBM Austin                                      =20
Istvan Novak - SUN
Chi-Shih Chang =E2=80=93 Kulicke &Soffa
Toshio Sudo - Toshiba, Japan
Paul Franzon - North Carolina State University
Gregory Taylor - Intel Oregon
Hartmut Grabinski - University of Hanover, Germany
John Prince -=80University of Arizona
Harold Hosack - Semiconductor Res. Corp.
Ryszard Vogel - Nokia, Finland
Lewis Terman - IBM Watson Research

Workshop  will   be  held  at  the  Westin  Princeton, 201 Village   Blvd.,
Princeton, NJ 08540. Telephone 609-452-7900, FAX : 609-452-1223. To learn
 more   about  the  hotel,  make  reservations  or  get  directions  go  to
www.westin.com/princeton.  The  hotel  is  holding a block of rooms for the
meeting at  the special rate of $145 plus tax, single or double occupancy. =
In
order to receive this special conference rate, reservations must be made by
 5:00 PM EST, October 4, 2003. Reservations made after this date will be on=
 a
space and rate available basis. Be sure to indicate that you are attending
the EPEP Meeting. Additional information may be obtained from the workshop
chairs: Alina Deutsch, deutsch@xxxxxxxx and Madhavan Swaminathan,
 madhavan.swaminathan@xxxxxxxxxxxxx,  and the workshop administration, Paul
Baltes, epd@xxxxxxxxxxxxxxxxx All attendees must register by September 12,
2003  using the EPEP=E203 website at www.epep.org in order to assure that t=
he
workshop is being held. On-site registrants will be admitted depending on
availability of seating.

The following  talks are planned:
A=B7   Future Directions in Supercomputing, George Chiu, IBM Corporation

B=B7   Clock Distribution for Multi-GHz Microprocessors, Frank O=E2=80=99Ma=
hony,
     Stanford University

C=B7   Mixed-Signal Measurement Circuits for Embedded Test Access, Gordon
     Roberts, McGill University
.
D=B7   Package Level EMI Study, Y. L. Li, Intel Corporation

E=B7   The Challenge of Correct Modeling and Testing of Advanced High-Speed
     Multi-Pins Connectors, Luc Martens, University of Ghent

F=B7   CAD Tool Requirements for Next Generation Signal Integrity, Howard
     Smith, IBM Corporation

G=B7   Toward Full-Chip Analysis with Electromagnetic Accuracy: Needs,
     Challenges, and Current State of the Art, Andreas Cangellaris,
     University of Illinois

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