[SI-LIST] Analog/Digital vss connection for a PLL IC

From: Bi Han <mike_bihan@xxxxxxxxxxxx>
To: List` Si <si-list@xxxxxxxxxxxxx>
Date: Thu, 27 Apr 2006 06:32:38 -0700 (PDT)

Hi, folks:
   
  Just wondering about an old question. 
   
  There is a PLL chip, it has one pair of analog vdd/vss and one pair of 
digital vdd/vss. We will seperate vdds on chip and only connect them on the 
board level.
   
  My question is that shall we tie the analog vss with digital vss together on 
the chip? 
   
  I've ever seen different types of answers on different forums, ppt, papers. 
Anyone suggest a one-stop document for that kind of conundrum?
   
  thanks,
  Han
   
                
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Follow-Ups:

[SI-LIST] Re: Analog/Digital vss connection for a PLL IC
From: Faraydon Pakbaz

[SI-LIST] Analog/Digital vss connection for a PLL IC

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