[SI-LIST] Re: Agenda, IBIS Summit at DesignCon for Feb. 5, 2009

The only problem is that it conflicts with my paper to be given Thursday 
:) Might be a nice short break from the day long meeting.

Doug

Mirmak, Michael wrote:
> Please join us for the free IBIS Summit at DesignCon in Santa Clara next week!
>
> Presentation materials will be available on-line after the event.
>
> -----------------------------------------------------------------------
>
>                       AGENDA - IBIS SUMMIT MEETING
>                        Thursday, February 5, 2009
>
>                      Santa Clara Convention Center
>                         Santa Clara, California
>
>                    Room: 209 and 210 in the Convention
>                   Center, Second Floor (look for signs)
>
> -----------------------------------------------------------------------
>
> 8:00 AM     Refreshments & Sign In
>
> 8:30 AM     Official Opening
>             - Welcome to Summit
>             - Introductions
>             - Opens for Issues & Discussion Topics
>
> 8:45 AM     Chair's Status Report
>             Michael Mirmak, Intel Corporation
>
> 9:00 AM     How IBIS Models Relate to SI, PI, and EMI-EMC
>             Roy Leventhal, Leventhal Design & Communications
>
> 9:30 AM     EMI Parameters for IBIS
>             Guy de Burgh, EM Integrity
>
> 10:00 AM    BREAK
>
> 10:15 AM    Mixed Mode Parameter Support: Definitions and Transformations
>             Vladimir Dmitriev-Zdorov,  Mentor Graphics Corporation
>
> 10:45 AM    Primer on Mixed-Mode Transformations in Differential
>             Interconnects
>             Yuriy Shlepnev, Simberian
>
> 12:00 PM    LUNCH - (Hosted by Cisco Systems)
>             Pre-registration required
>
> 1:00 PM     Using IBIS EBD for DDR2/DDR3 Module Board
>             Lance Wang, IO Methodology
>
> 1:30 PM     IBIS Quality at Xilinx - The State of the Onion
>             David Banas, Xilinx
>
> 2:00 PM     IBIS DNA: Decoding the Quality Gene
>             Tim Coyle, Signal Consulting
>
> 2:45 PM     BREAK
>
> 3:00 PM     Capacitance Compensation
>             Bob Ross, Teraspeed Consulting Group
>
> 3:30 PM     Creating Broadband Analog Models for SerDes Applications
>             Todd Westerhoff*, Doug White**, Adge Hawes***, Walter Katz*,
>             and Mike Steinberger*; *Signal Integrity Software (SiSoft),
>             *Cisco Systems, and ***IBM
>             (Presented by Todd Westerhoff*)
>
> 4:00 PM     Open Discussion
>
> 4:45 PM     Concluding Items
>             - Next Open Forum Meeting: February 20, 2009
>             - DATE 2009: April 23, 2009, Nice, France
>
> 5:00 PM     End of Meeting Room Availability
>
> ------------------------------------------------------------------
>
> If you plan to participate, please register with the information below:
>
>    Name:
>    E-mail address:
>    Company:
>    Telephone:
>
> Send to: Syed Huq <huqs@xxxxxxxxx>
>
> Sponsors:   Cisco Systems, DesignCon, IBIS Open Forum
>
> DesignCon:  February 2 - 5, 2009
>             Santa Clara Convention Center
>             Santa Clara, California
>             See http://www.designcon.com/ for more information.
>
> LIST OF NEARBY HOTELS
>
>   See http://www.designcon.com/2009/hotel_travel/ for
>   travel directions, hotels and other information.
>
> ------------------------------------------------------------------
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>
>   

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     ___          _            Doug Smith
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