[SI-LIST] Re: Advice

Justin,

As it was already pointed out, the discontinuity created by the 
DC-blocking capacitor could be minimized by combining with existing 
features on the board and possibly reduce the number of vias in the 
chain.  This having said, assuming that the discontinuity created by the 
capacitor is identified and kept the same as you move it along the trace 
in module 1, the result very well may depend on the location.  As it was 
pointed out earlier to a similar question, if we change the sequence 
(reshuffle the order) of linear reciprocal building blocks, the 
end-to-end result (voltage transfer function and input reflection) stays 
the same only under special circumstances.

Regards,

Istvan Novak
SUN Microsystems


Smith, Justin D. wrote:
> I'm working on a 6.25Gbps channel SI issue with a constraint that is not 
> ideal. We have a legacy issue which requires that we put decoupling caps on 
> the "transmit" side of a transmission line instead of the receive side (where 
> we'd like them). This must be done to maintain "backwards compatibility" with 
> MODULE 2 that does not have decoupling on the receiver side.
>
> That said, we have this type of setup:
>
> ==================================================================
> #      MODULE 1              BACKPLANE           MODULE 2        #
> # XMT     DCPL        BP.                 BP.               RCVR #
> # |\      CAP         Conn     Trace      Conn              |\   #
> # | \_____||__________[  ]________________[  ]______________| \  #
> # | /     ||          [  ]                [  ]              | /  #
> # |/                                                        |/   #
> =============================Fig 1================================
> (hope that cheesy ascii graphic comes through)
>
> Some questions arise that I would value the SI-LIST opinion on:
>
> 1)Where to put the decoupling cap with the constraint that we have to put it 
> on MODULE 1, which is the XMT side of the overall channel?
>
>       a. Near to the transmitter (possibly greater reflected power into the 
> transmitter?)
>       b. Near the BP connector (as close to the RCV as we can? makes the 
> discontinuity more capacitive - but "lumps" issue with connector 
> discontinuity).
>       c. In the middle (distribute the discontinuities along the path - 
> possibly results in multiple reflections?).
>
> 2) Knowing that the backplane trace is very short (~1.5") does that effect 
> how you'd advise? 
>
> 3) Parameters that I can work with are the length of the trace from FPGA to 
> connector on the module, location of the cap, and cap value/size.
>
> We have Hyperlynx as a SI tool. Thoughts? Anybody ever dealt with an issue 
> like this before?
>
> -justin
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