[SI-LIST] Re: Advice

Generally, I found that having the caps close to the receiver (or
transmitter in this case) allows the fewest vias and the shortest via
stubs. The pin escape from from the IC can go microstrip to the caps and
then via down to a stripline layer close to the bottom of the PCB and on
to the connector pin via. At this data rate you may want to tune the cap
pads in a full wave simulator to minimize the cap discontinuity. 

I think it's more important to minimize the magnitude of the resonances
from the discontinuities than to worry about how/where they're lumped
together. I've read that the biggest impact with having the caps near
the receiver is that it can slow the edge rate slightly. Having them on
the transmitter side offers better protection to shorts/faults.

Mike

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Smith, Justin D.
Sent: Monday, July 20, 2009 2:20 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Advice

I'm working on a 6.25Gbps channel SI issue with a constraint that is not
ideal. We have a legacy issue which requires that we put decoupling caps
on the "transmit" side of a transmission line instead of the receive
side (where we'd like them). This must be done to maintain "backwards
compatibility" with MODULE 2 that does not have decoupling on the
receiver side.

That said, we have this type of setup:

==================================================================
#      MODULE 1              BACKPLANE           MODULE 2        #
# XMT     DCPL        BP.                 BP.               RCVR #
# |\      CAP         Conn     Trace      Conn              |\   #
# | \_____||__________[  ]________________[  ]______________| \  #
# | /     ||          [  ]                [  ]              | /  #
# |/                                                        |/   #
=============================Fig 1================================
(hope that cheesy ascii graphic comes through)

Some questions arise that I would value the SI-LIST opinion on:

1)Where to put the decoupling cap with the constraint that we have to
put it on MODULE 1, which is the XMT side of the overall channel?

        a. Near to the transmitter (possibly greater reflected power
into the transmitter?)
        b. Near the BP connector (as close to the RCV as we can? makes
the discontinuity more capacitive - but "lumps" issue with connector
discontinuity).
        c. In the middle (distribute the discontinuities along the path
- possibly results in multiple reflections?).

2) Knowing that the backplane trace is very short (~1.5") does that
effect how you'd advise? 

3) Parameters that I can work with are the length of the trace from FPGA
to connector on the module, location of the cap, and cap value/size.

We have Hyperlynx as a SI tool. Thoughts? Anybody ever dealt with an
issue like this before?

-justin
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