[SI-LIST] Re: Address bus simulation

Hi Bob,

Simply put, you will be better served utilizing
scheme B.  If in fact your timing is tight long 
runs of ones or zeros followed by a single instance
of the opposite may yield longer timing that could
cause you problems.  A pseudo random sequence can 
help model this behavior.  If your tool limits you
to only a pulse imput, you may wish to extend the
period of the pulse in order to get a true picture 
of the settling time.  

Be careful about sweeping statements about buses 
not running at the rate of the clock.  In todays 
world of dual edge clocking and multi-level signalling,
things may actually 'worse' than simply toggling at
the rate of the clock.

When working through your timing calculations, remember
that clock to out on the device is specified in a 
given test load.  Adding your simulated flight time 
number to this test load number will give an overly large 
number which may indicate set up times are violated 
when they aren't or that hold time is OK when it isn't.
A number of the tools have the ability to subtract out
this number, but if you are doing things manually you
need to be aware of this.

I hope that this helps.

MG

-----Original Message-----
From: Bob Patel [mailto:whizplayer@xxxxxxxxx]
Sent: Tuesday, October 16, 2001 10:31 PM
To: si_list
Subject: [SI-LIST] Address bus simulation



Hi! I don't know if the above topic was discussed
before because I could not find it in the archives on
a quick scan.
Say, we need to do find out whether we can run the
address bus to two loads in Star configuration with
clock at 200Mhz. Now, first the address bus will be
not running at this frequency clock frequency.
So, in terms of simulation what should be the approach
a) Run simulation with pulse source at 200Mhz--->Not
true picture
b)Run simulation with random bit pattern?
I want to know what would be appropriate in simulating
this?
Thanks in advance
Bob

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