[SI-LIST] Re: About jitter simulation

Herry:

Please check with the following latest reference in this area:

Prentice Hall "Jitter, Noise, and Signal Integrity at High Speed",
http://www.amazon.com/Jitter-Integrity-High-Speed-Prentice-Semiconductor
/dp/0132429616

with ISBN-13: 978-0-13-242961-0
     ISBN-10:     0-13-242961-6

Pay special attention on chapters 7, 8, 9 10. You will find most of the
answers there.=20

Good luck!=20

Thanks!

Mike

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of herry_06
Sent: Friday, December 21, 2007 9:39 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] About jitter simulation

Hi, Experts,
=20
    The vendor often provides PK to PK jitter parameter of PLL, but as
we know, a reference clock on board will be feed to PLL via ASIC package
and a input IO buffer, so we how to do simulation to get reference clock
jitter requirement. could you help to give simulation methodology?
thanks!
=20
Regards
Henry
=20
=20
=20
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