[SI-LIST] About jitter simulation

Hi, Experts,
 
    The vendor often provides PK to PK jitter parameter of PLL, but as we know, 
a reference clock on board will be feed to PLL via ASIC package and a input IO 
buffer, so we how to do simulation to get reference clock jitter requirement. 
could you help to give simulation methodology? thanks!
 
Regards
Henry
 
 
 
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