[SI-LIST] AW: trouble simulating with AC coupling capacitors in topology
- From: "Havermann, Gert" <Gert.Havermann@xxxxxxxxxxx>
- To: "Roopesh Badala" <roopesh.badala@xxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Fri, 8 Jul 2011 13:42:33 +0200
Hi Roopesh,
I don't know the Cadence tool, but in other simulators you have to initialize
the caps, saying that you have to set them the a stable dc voltage prior to
simulation. If you don't, then you have to wait for the caps to load, and that
will take several miliseconds or thousends of bits.
At the start of the simulation, the caps are unloaded, resulting in a DC offset
of the signal. The receiver can't find the Bit crossing, and there is no
result. Try to plot the bits before and after the caps to find out.
BR
Gert
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-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im
Auftrag von Roopesh Badala
Gesendet: Freitag, 8. Juli 2011 13:25
An: si-list@xxxxxxxxxxxxx
Betreff: [SI-LIST] trouble simulating with AC coupling capacitors in topology
Hi All,
I am trying to simulate a topology which has AC coupling capacitors in it.
Using Cadence Allegro PCB SI tool set , i am unable to get the expected output.
but when I simulate the same topology by removing the AC coupling capacitors in
signal path, I get a perfect waveform.
Is this a tool limitation..? can some body suggest me if they have faced
similar issue.
Thank you
Roopesh
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- » [SI-LIST] AW: trouble simulating with AC coupling capacitors in topology - Havermann, Gert
