[SI-LIST] AW: signal layer between pwr/gnd layers
- From: "Sol Tatlow" <Sol.Tatlow@xxxxxxxxxxxxxxx>
- To: <Tegan.Campbell@xxxxxxxxxxx>, "silist" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 19 May 2004 14:46:43 +0200
Hi Tegan,
just one comment: a board stackup should be symmetrical. It may be
that yours is, and that you already know this (as I only see the 6
layer part of it), but be aware that asymmetrical layer stackings can
lead to serious warping of boards.
The worst example I saw of this was a customer of ours, who (before
becoming our customer!) had a board made by a competitor with the
following stack:
top-G-P-G-P-S-S-S-S-bottom
Quite apart from it being an SI disaster, this asymmetry (even if the
cores and prepregs are symmetrically ordered, in terms of thicknesses) =
of
4 solid planes on one side will lead to MEGA bowing when the board is =
then
soldered, due to differences in thermal expansion coefficients - in the
case of our customers, all boards had to be junked, since the warping
stress caused the fracturing of many internal via-plating connections,
rendering them useless.
Results might not be so drastic if the asymmetry is only slight, but I
would avoid it if possible!
____________________________________
Sol Tatlow, M.Eng. (Oxon)
ProDesign Electronic & CAD Layout GmbH
Product Developer
Albert-Mayer-Str. 16
D-83052 Bruckmuehl
Phone: +49 (0) 8062-808-302
Fax: +49 (0) 8062-808-333
Mailto:sol.tatlow@xxxxxxxxxxxxxxxxxxxx
www.prodesign-europe.com
____________________________________=20
-----Urspr=FCngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
Im Auftrag von Tegan Campbell
Gesendet: Dienstag, 18. Mai 2004 23:22
An: silist
Betreff: [SI-LIST] signal layer between pwr/gnd layers
All,
In trying to remove two layers from a 16 layer PCB I came up with a =
question
I don't know how to answer short of building a board, which there is not
time for.
I have closed the loop on simulation/modeling vs measurement for a PDS =
with
embedded capacitor using a 4 mil dielectric and capacitor array. I want =
to
say thank you to Sun and Xilinx for the excellent work and papers they =
have
published in the public domain on the subject.
Now, I am having trouble working out what would happen if I insert a =
signal
layer in between the planes. I need three signal layers to be =
referenced to
a pwr/gnd pair, and that currently takes six layers(G-S-S-P-G-S). If I =
can
insert a signal routing layer between pwr and gnd, it drops to five
layers(S-P-S-G-S). This happens on two different pwr rails. My first
reaction is the only difference would be the ~doubling of the distance
between the planes. I can decrease this effect by using 3 mil cores. =20
After thinking a while longer, it seems like there would be other
differences from the copper in between the planes. It seems like I =
should
be able to minimize the effect by using special spacing rules in the =
signal
layer between the planes to maximize the ratio of dieletric area to =
copper.
I think this would make the discontinuities in the dielctric(the copper
traces) insignificant.
I have not found a discussion of this specific PDS topic in the =
archives,
and I apologize in advance if I am repeating something that has already =
been
discussed.
Any input or thoughts are appreciated, thank you for your time.
Tegan Campbell
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