[SI-LIST] AW: Simulation problems with SSTL2 IBIS model (TI CDCV850)


Hi all,
Thank you very much for your prompt response.

Well, I think it is difficult to discuss something when
you don't know any details about the used models and=20
simulation tools. So, here they are.

For the simulation I used the following IBIS model
which can be downloaded from the TI website at:

CDCV850 IBIS Model (SCAM025, 49 KB - Updated: 06/20/2002)
http://www-s.ti.com/sc/psheets/scam025/scam025.ibs


TL: Z0=3D60Ohm, Td=3D0.5ns, Clock Frequency=3D100MHz
|\ Y0    ____
| \-----|____|---|=20
|  \      TL     |_
|  /           | | |  60R
| /      _TL_    |_|
|/=B0-----|____|---|=20
   Y0-
 =20
 Y0-: CDCV850_DOUT, Y0: CDCV850_DOUT=20

As I mentioned in my previous email, I performed the simulation=20
with two common simulation tools. These tools were Hspice 2002.2=20
and SpecctraQuest 14.2. I've also performed the same simulation=20
with older releases, but they show all the strange behavior.
The output signals from Y0 and Y0- cross near the low voltage=20
state instead of in the middle of the high and low state.

From my point of view it seems, that SpecctraQuest as well as=20
Hspice have problems to compute the correct waveforms,=20
because I have compared these results with HyperLynx (Innoveda),=20
Hot-Stage (Zuken), XTK and a simulation result based on an Hspice=20
transistor level model. These results look quite well.


Maybe someone of you has an idea about the differences in=20
handling IBIS files or what I should do to get good=20
simulation results.


Many thanks,
Dirk.
=20



> -----Urspr=FCngliche Nachricht-----
> Von: Linnenbruegger Dirk=20
> Gesendet: Donnerstag, 19. September 2002 13:37
> An: 'si-list@xxxxxxxxxxxxx'
> Betreff: [SI-LIST] Simulation problems with SSTL2 IBIS model=20
>=20
>=20
>=20
>=20
> Hi SI-List members,
>=20
> I have performed some simulations using an IBIS=20
> model of a differential clock buffer and I wonder=20
> about the strange waveform behavior.=20
> The simulations have been computed with two very=20
> common simulation tools.
>=20
> The output signals cross near the low voltage state=20
> instead of in the middle of the high and low state.
> Furthermore high ringing occurs although the=20
> transmission lines are terminated properly.
>=20
> After some investigations of the IBIS file I found=20
> out, that the simulation results look much better,=20
> if the [ramp] data will be used instead using the=20
> [rising/falling waveforms].
>=20
> But, of course these simulation results based on the=20
> ramp data don't correlate very well to the reference=20
> waveforms, which are based on an Hspice transistor=20
> level model. Therefore I tried to get some more=20
> simulation results which have been computed with some=20
> other tools. I was really surprised, that the new=20
> results of the other tools look quite well.
>=20
> From my point of view it seems, that the IBIS file is=20
> OK and that there might be some problems in our tools=20
> to handle this kind of IBIS file.
>=20
> So, I would like to know if someone of you had similar=20
> problems or an idea how to solve this problems.
>=20
>=20
> Thanks
> Dirk Linnenbruegger =20
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