[SI-LIST] Re: AW: Re: ESD on center pin of 6VDC jack input.
- From: Doug Smith <doug@xxxxxxxxxx>
- To: davidjp@xxxxxxx
- Date: Wed, 19 Dec 2007 22:53:45 -0800
Hi David and the group,
I would like to add one point to David's discussion. A transmission line
pulser does not adequately model a cable discharge event (CDE). In
addition to the transmission line discharge there is an initial spike
that appears the same as the IEC test. After the initial spike there is
a transmission line discharge followed by ringing at a frequency
dependent on cable length.
See my article that I wrote back in 2002 on this at:
http://emcesd.com/tt2002/tt010102.htm
Doug
Pommerenke, David wrote:
>Group,
>
>Judging if testing a connector with an ESD simulator is needed requires =
>detailed knowledge on the port's location and use model. The amended IEC =
>61000-4-2 explains quite well when PIN testing is required.
>
>However, if a cable is plugged into a connector and a very severe metal =
>to metal discharge can occur. This type of discharge (named =93Cable =
>Discharge Event=94) is not the reference event for the IEC 61000-4-2, =
>the standard is based on the discharge of a human via a small piece of =
>metal like a key (=93human-metal ESD=94).
>
>If a portable EUT fails (soft- or hard-error) the moment a cable is =
>plugged into a connector I would strongly suggest analyzing the root =
>cause of the problem. For portable equipment CDE events will be quite =
>likely. In most cases I would discourage adding rubber caps or alike to =
>avoid testing this test points.=20
>
>Using a transmission line pulser as injection device models CDE quite =
>well, but an IEC 61000-4-2 generator will give you an indication of the =
>robustness, at least for soft-errors.
>
>There are many ways to solve such problems, filtering, re-routing, =
>software. But all solutions need an understanding where to apply them. =
>This requires understanding the root cause: hich net is affected and =
>which IC will be disturbed. In our research we use local scanning for =
>locating sensitive areas on PCBs or in ICs. Details of the method are =
>explained in:=20
>
> Finding the root cause of an ESD upset event
> Pommerenke, D; Jayong Koo, Giorigi Muchadze
> DesignCom 2006, Santa Clara, Feb. 2006
>
>
> http://web.mst.edu/~davidjp/publications.html
>
> or
>
> http://web.umr.edu/~davidjp/publications.html
>
>Regards,
>
>David Pommerenke
>
> EMC laboratory, University Missouri Rolla (soon: Missouri Science and =
>Technology MST)
> 573 308 2019 / 573 341 4531=20
>
>
>
>
>
>
--
-------------------------------------------------------
___ _ Doug Smith
\ / ) P.O. Box 1457
========= Los Gatos, CA 95031-1457
_ / \ / \ _ TEL/FAX: 408-356-4186/358-3799
/ /\ \ ] / /\ \ Mobile: 408-858-4528
| q-----( ) | o | Email: doug@xxxxxxxxxx
\ _ / ] \ _ / Website: http://www.dsmith.org
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- Follow-Ups:
- [SI-LIST] CML versus ECL/PECL
- From: wolfgang . maichen
- References:
- [SI-LIST] Re: ESD on center pin of 6VDC jack input.
- From: Ken Cantrell
- [SI-LIST] AW: Re: ESD on center pin of 6VDC jack input.
- From: Pommerenke, David
Other related posts:
- » [SI-LIST] AW: Re: ESD on center pin of 6VDC jack input.
- » [SI-LIST] Re: AW: Re: ESD on center pin of 6VDC jack input.
- [SI-LIST] CML versus ECL/PECL
- From: wolfgang . maichen
- [SI-LIST] Re: ESD on center pin of 6VDC jack input.
- From: Ken Cantrell
- [SI-LIST] AW: Re: ESD on center pin of 6VDC jack input.
- From: Pommerenke, David