[SI-LIST] ASIC design, DDR2 project in Sunnyvale

Hello guys. I realize that this is more of a signal integrity specific
mailing list, but I did want to let you all know that I have a client in
Sunnyvale who is looking for an ASIC designer with a strong DDR2
background. This could be either a straight consulting job, or a
contract to hire position. If anyone is qualified and interested, please
contact me directly. If not, please let me know if you know of anyone
whom would be.

Regards,

Kevin D. Pierpoint
Branch Manager/Technical Recruiter
Oxford & Associates, Inc.
(408) 245-3915 x111=20

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Bill Wurst
Sent: Tuesday, March 25, 2008 7:47 AM
To: icer world
Cc: SI LIST
Subject: [SI-LIST] Re: DDR2 design issues?

Hello Icer,

 From the way you have phrased your question, referring to terminations
as "pull-ups," I suspect that your background is digital design and not
SI.  The design of something as complex as a DDR2 interface is not
something that could be readily communicated in an email response, even
to someone already skilled in the practice of SI.  I would suggest
subcontracting out the design.  There are a number of folks on this list
who may be in a position to take on additional work at this time, if
that is a direction you wish to pursue.

Best regards,
     -Bill


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icer world wrote:
> hello everyone:
>     I will use DDR2 in my design ,and the DDR2 controller surpport ODT

> function  .I think if I take use of ODT function ,pull-up resistor=20
> connected  to VTT (0.5VDD) will not be needed in all the signal
pins.But I got a demo design from chip applier that use 50ohm pull-up
resistor connected  to VTT in all the signal pins.Can anyone tell me
whether pull-up resistor connected  to VTT is needed in my design?If
needed,please tell me how to design it ,thanks!
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