[SI-LIST] ASIC characterization

Hello Istvan,=20

Sorry for not replying to your question earlier; I was out of the office
for the last two days.  To answer your question, there are two
approaches.  First, I should say that this would be a challenge that we
would love to take on -- having 20 major customers.  The company
certainly will increase the head count and lab resources as much as
possible to match the work-load (which the company is already doing, as
the 1st solution).  But you are right.  We cannot increase the lab size
and the head count 20X.  What we will have to do (as the 2nd solution)
is to go through the applicable specs and come up with a top level spec
that supersedes all the other specs.  For example, the 12G TX jitter
spec is much more stringent than the 6G TX spec, and the OIF long-reach
compliance channel (40 inches FR4 trace) generates much more ISI and
amplitude attenuation than the short-reach channel.  But for specs with
data-rate non-multiple of each other (8.5G Fibre Channel vs. 6.375G
OIF), we will have to do completely separate characterizations.  It
further gets complicated when two specs both require 0.7UI RX jitter
tolerance but with quite different RJ, DJ, SJ, and BUJ content.  We may
have to get a waver from customers to accept one spec over another,
knowing that different types of jitter will exercise the CDR differently
inside the receiver.  There is no quick, easy, and clean solution, so we
will have to approach this from both ends -- adding resources and
finding superseding specs.  But this will be a problem that we love to
take on.  Of course, in a business environment, larger customers
certainly have more swaying power than smaller ones, and management will
prioritize accordingly. =20

Thanks,=20
=20
George=20
=20

Note: Effective October 14, 2006, My LSI Logic Email address will change
to: george.tang@xxxxxxx

Please update address books and email lists accordingly.


-----Original Message-----
From: Istvan.Novak@xxxxxxx [mailto:Istvan.Novak@xxxxxxx]=20
Sent: Friday, March 23, 2007 8:10 PM
To: Tang, George
Cc: si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Jitter transfer vs. accumulation

George,

I did not mean meeting multiple specifications simultaneously, I meant=20
what if
20 of your customers are asking for characterization data for 20
different
standards.  And assume all new designs.  Dont get me wrong: I agree with

you
that you cannot do the characterization for all of them due to resource
limitations.  My point was that we all need to work hard from both ends
(test/measurements and silicon design) to get relief to this challenge.

Regards,
Istvan Novak

Tang, George wrote:

>Istvan,=20
>
>Well, not completely true.  If you have to meet 3 or 5 specifications
>simultaneously, we could always tighten the spec to meet the overall
>requirements.  But you would have to live with those specs for all your
>applications, even though some of the applications could survive with a
>lesser spec.  It's the opposite that we fear most: If you ask the
>question that "I have a 10 year old system with noisy power supplies,
>but I want to upgrade just one ASIC in my system with your chip without
>doing field replacement for anything else in the system for cost
>reasons....."  In that case, we just plug our ears.   :) =20
>
>=20
>Regards,
>=20
>George=20
>=20
>
>Note: Effective October 14, 2006, My LSI Logic Email address will
change
>to: george.tang@xxxxxxx
>
>Please update address books and email lists accordingly.
>
>
>-----Original Message-----
>From: Istvan.Novak@xxxxxxx [mailto:Istvan.Novak@xxxxxxx]=20
>Sent: Friday, March 23, 2007 6:55 PM
>To: Tang, George
>Cc: Alfred P. Neves; weirsi@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
>Subject: Re: [SI-LIST] Re: Jitter transfer vs. accumulation
>
>George,
>
>This discussion looks like a Gaussian process, with time it grows=20
>unbounded :-) .
>
>Anyway, I see and appreciate your point about the amount of time and=20
>effort to do
>a full characterization for all possible standards.  However, this=20
>brings up a generic
>issue. And what I am going to say is not meant to be an offense to you:

>you have the
>knowledge and capabilities to give the customer the data they need;=20
>GIVEN that
>company resources permit that.  From what you say I sense that even if
>your
>chips were so popular and succesful that customers would want to use=20
>them for
>all applicable standards, the full characterization still would not=20
>happen due
>to the obvious reasons of finite resources.   This, unfortunately,=20
>leaves the end user
>many times with inadequate input data and doing a proper design becomes
>hard, if not a guesswork. =20
>
>At SUN we use clock sources, and chips with various SerDes interfaces
>from a number of respectable vendors.  Getting any data on how the=20
>supply rail
>noise impacts output jitter in a clock source or SerDes, or what=20
>rail-noise limit
>do we need to keep to achieve the specified jitter, is the exception,=20
>not the norm.
>I can imagine the pain of designers in smaller companies, not having
the
>
>same leverage.
>
>I hope the industry will continue to work hard on both fronts:
improving
>
>the test and
>measurement processes/instruments so that characterization becomes=20
>faster/easier,
>and improving chips so that they are less sensitive or become better=20
>characterized
>for rail-noise sensitivity.
>
>Regards,
>Istvan Novak
>
>
>
>Tang, George wrote:
>
> =20
>
>>Istvan,=20
>>
>>The SerDes market has about 20 different specs (Fibre Channel 1G 2G
4G,
>>SAS/SATA 1.5G 3G 6G, PCIE 2.5G 5G, OIF 3G 6G, XAUI, CX4, GPON, Gigabit
>>Ethernet 1G 10G, FBDimm, Hypertransport, SONET, SPI, SFI, CPRI, etc).
>>To do PVT testing for the required conditions and skew lot for all the
>>different standards will take years.  The data sheet cannot possibly
>>include the number for all the different specs.  We characterize to
>>   =20
>>
>what
> =20
>
>>the customer requests; otherwise we will be wasting time on those
specs
>>that no one cares about. =20
>>
>>Thanks for asking,=20
>>
>>George=20
>>
>>
>>Note: Effective October 14, 2006, My LSI Logic Email address will
>>   =20
>>
>change
> =20
>
>>to: george.tang@xxxxxxx
>>
>>Please update address books and email lists accordingly.
>>
>>
>>-----Original Message-----
>>From: Istvan.Novak@xxxxxxx [mailto:Istvan.Novak@xxxxxxx]=20
>>Sent: Friday, March 23, 2007 1:21 PM
>>To: Tang, George
>>Cc: Alfred P. Neves; weirsi@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
>>Subject: Re: [SI-LIST] Re: Jitter transfer vs. accumulation
>>
>>George,
>>
>>I like your approach.  So you are saying if the user needs your chip,
>>for instance, to run XAUI, you can tell the user what is the maximum
>>allowed noise or periodic disturbance on the various analog pins.  Do
>>you state those numbers also on the data sheet (for selected
standards)
>>or is the characterization excercise on a per-request basis?
>>
>>Regards,
>>Istvan
>>
>>
>>
>>Tang, George wrote On 03/23/07 15:59,:
>>=20
>>
>>   =20
>>
>>>Well, the +/- 5% is the generic spec.  Depending on what applications
>>>you are interested in, say OIF 6G, or XAUI, or GPON, etc, all having
>>>different jitter specs, your power spec will be different for
>>>  =20
>>>
>>>     =20
>>>
>>different
>>=20
>>
>>   =20
>>
>>>applications.  There is no point in making everyone to meet the
>>>  =20
>>>
>>>     =20
>>>
>>toughest
>>=20
>>
>>   =20
>>
>>>specs when his application does not require it.  We can (and do)
>>>characterize to your specific application with a certain power noise
>>>tolerance to demonstrate the chip performance and give you the
>>>confidence level you require. =20
>>>
>>>Thanks,=20
>>>
>>>George=20
>>>
>>>     =20
>>>
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