[SI-LIST] Re: AC cap placement on Clocks
- From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
- To: "icer world" <icermail@xxxxxxxxx>, "Sam Pete" <cygnul@xxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Thu, 22 Oct 2009 06:39:52 -0700
Form an SI point of view, it does not matter where along the path the
capacitors are placed.
> [Original Message]
> From: icer world <icermail@xxxxxxxxx>
> To: Sam Pete <cygnul@xxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> Date: 10/21/2009 8:48:26 PM
> Subject: [SI-LIST] Re: AC cap placement on Clocks
>
> It's hard to say where the AC cap should be placed ,so you'd better do a
simulation if you have device models .
> I'm in doubt that why you use the AC coupling manner since the driver and
the receiver are both LVDS level.
>
>
>
> ________________________________
> From: Sam Pete <cygnul@xxxxxxxxx>
> To: si-list@xxxxxxxxxxxxx
> Sent: Thu, October 22, 2009 7:22:17 AM
> Subject: [SI-LIST] AC cap placement on Clocks
>
> Hi All,
> I have a situation like this:
> LVDS Driver, ac cap, LVDS receiver (internal term) 156MHz clock.
> |>-----------------||----------------|>
> |>-----------------||----------------|>
>
>
> What is the optimum place to put coupling cap when the clock is
ac-coupled.
> Should it be close to driver or should it be close to receiver.
>
> From my understanding, the discontinuity should not be visible to the
electrical length of the signal. Having said that, ac cap should be as
close as possible to Driver.
>
> please share your thoughts.
>
> Thanks
> Sam
>
>
>
>
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