[SI-LIST] Re: 6 layers stackup
- From: "Mangipudi, Prasad" <Prasad_Mangipudi@xxxxxxxxxxx>
- To: 'giorgio ravesio' <info@xxxxxxxxxxxxxxxx>, "'Raju, Ramakrishna'" <ramakrishna.raju-Contractor@xxxxxxxxxxxxxxx>, 'I Ilamparidhi' <ilam.paridhi@xxxxxxxxx>
- Date: Fri, 25 Apr 2008 15:36:17 -0700
Giorgio,
You are better off using S-G-S-S-G-S with local power pours on signal layer=
s with dielectric height adjustment between layers 3/4(in the center betwee=
n signal layers) for board thickness. This way you can control impedance f=
or all signal layers, and provide ground reference for all signals.
Your stackup is not popular as there is no ground reference for signals on =
layers 4 and 6 and the P/G planes are separated. It may still work if the d=
esigns are not very high speed or not many signals are switching at high sp=
eed. You are better off using layer 1 for critical nets.
Best regards,
Prasad
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On=
Behalf Of giorgio ravesio
Sent: Friday, April 25, 2008 1:35 PM
To: Raju, Ramakrishna; I Ilamparidhi
Cc: David Instone; Saoer Sinaga; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: 6 layers stackup
Hi all,
Is there some particolar reason because nobody propose the usal S-G-S-S-P-=
S stackup?
I did use this specific stackup several times in boards with components mou=
nted on top of the board, routing the critical nets in layer 3 and 4 and ro=
uting all the least critical nets on layer 1 and 6.
I agree that keeping Power and Ground Layer as close as possible is indeed =
a nice choise (i.e S-S-G/P -P/G -S S) but this choice means an appreciable =
difference in the width of any traces routed in layer 1/6 with respect laye=
r
2/5 in order to sustain an invariable Zo between routing layers.
Best regard.
Giorgio Ravesio
url : grconsulenze.com
mail: info@xxxxxxxxxxxxxxxx
----- Original Message -----
From: "Raju, Ramakrishna" <ramakrishna.raju-Contractor@xxxxxxxxxxxxxxx>
To: "I Ilamparidhi" <ilam.paridhi@xxxxxxxxx>
Cc: "David Instone" <dave.instone@xxxxxxxxxx>; "Saoer Sinaga"
<saoer.sinaga@xxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
Sent: Friday, April 25, 2008 7:47 AM
Subject: [SI-LIST] Re: 6 layers stackup
Hi Ilam,
Good question,
In most of the PCB Designs Ground bounce is caused by the simultaneous swit=
ching of drivers in an IC package and it may cause functionality as well as=
EMI related issues.
Ground Bounce presents a situation where the ground reference system is not=
immediate to the Ground chip pins.
Let me know weather I have answered your question.
Regards,
Ram
________________________________
From: I Ilamparidhi [mailto:ilam.paridhi@xxxxxxxxx]
Sent: Friday, April 25, 2008 10:57 AM
To: Raju, Ramakrishna
Cc: David Instone; Saoer Sinaga; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: 6 layers stackup
Hello Ram,
Why do you say 'G' is better than 'P' for chip pins?
Please explain me.
Thanks
Ilam
On Thu, Apr 24, 2008 at 2:31 PM, Raju, Ramakrishna <ramakrishna.raju-Contra=
ctor@xxxxxxxxxxxxxxx> wrote:
Hi,
Apart from the previous threads, the basic idea to use G layer next to top =
layer is that the return path for the chip pins will be good compare to P l=
ayer.
Regards,
Ram
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of David Instone
Sent: Thursday, April 24, 2008 2:05 PM
To: Saoer Sinaga
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: 6 layers stackup
I think your question is 'why have the G layer nearest the top of the board=
rather than the P layer?' Probably because the chips are generally on the=
top side of the board and having the the G layer nearest means your hi-spe=
ed racks can reference G rather than P without needing vias. Of course wit=
h a good decoupling referencing P rather than G might not be a problem, see=
previous threads on this list re referencing G or P. However, the G layer=
is generally one complete area over the board while the P layer must often=
be split into sections for different voltages; giving rise to problems whe=
re signal traces have to cross the splits
Regards
Dave Instone
+44 (0)1235 824963
OXFORD SEMICONDUCTOR LIMITED
25 MILTON PARK
ABINGDON
OXFORDSHIRE
OX14 4SH
Registered in England no 2733820
Registered Address: As above
Saoer Sinaga wrote:
> Dear all,
> May I know the reason why people would generally use S1 S2 G P S3 S4
> configuration for six-layer stackup? Why not S1 S2 P G S3 S4?
> Thanks.
>
> regards,
> Saoer
>
> On Wed, Feb 20, 2008 at 11:17 PM, Fernando Yuitiro Mori
<mori@xxxxxxxxxxxxx>
> wrote:
>
>
>> Hi,
>> I normally use S1 S2 G P S3 S4 for the 6 layers stackup. I need the 4
>> layer with 60 ohms, so there are some problem if I use S1 G S2 S3 P
S4?
>>
>> Regards,
>>
>> Fernando Mori
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I. Ilamparidhi
Design Engineer
Freescale Semiconductor India Pvt. Ltd.
Mobile No : +91-9999036561
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