[SI-LIST] Re: 50 ohm and 130 ohm on the same board

M, that is an interesting application model.  I think the prevailing wisdom 
would have been to use a lower impedance driver and transmission line to 
minimize the discontinuity caused by load capacitances.  What you did plays 
on paper.  I would be wary of how accurately the real loads match the line, 
especially with tolerancing, but if it worked, that is what counts.

Still 130 ohms seems like a value derived from a pair and not a single 
ended.  I think Prasad is in India, and we won't see a response until tonight.

Regards,

Steve.
At 05:00 PM 6/2/2004 -0600, msharpes@xxxxxxxxxx wrote:
>Although 130 Ohms seems on the high side, through some experience I can
>talk of designing higher impedance transmission lines (in the 100 Ohm
>neighborhood) for a fairly large distributed load.  So, the concept was
>that the capacitive nature of each of the distributed loads served to
>lower the characteristic along the line so much so in some cases that
>impedances of 80-100 Ohms were desired for a 50 Ohm 'effective'
>impedance.  The trick to doing this is to space the loads in an equal
>pitch with the pitch being something less than an inch for the
>transmission line to 'look' like something around 50 Ohms.  Now, this
>isn't portable to extremely fast designs, but we have had success with
>terminated transmission lines of this type with the right drive strength
>and source impedance to move 2V/ns at each load in a 3.3V system.
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of steve weir
>Sent: Wednesday, June 02, 2004 12:22 PM
>To: prasadsa@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: 50 ohm and 130 ohm on the same board
>
>
>S A, I agree with the poster who questions the 130 ohms in the first=20
>place.  Such a high impedance trace is an invitation to EMI.  That
>sounds a=
>=20
>lot closer to the odd mode impedance for a differential pair feeding
>STP=20
>and would correspond to 65 - 75 ohms even mode depending on how tightly
>you=
>=20
>couple. Before you go defining your board geometry, make sure your=20
>requirements are correct.
>
>Steve.
>At 08:39 PM 6/2/2004 +0530, saprasad wrote:
> >Hello All,
> >
> >I have a board with 2 sets of signal, the first set of nets need to be
>at
> >50ohm characteristic impedance and the other at 130ohm (single ended).
> >This is not practically possible due to manufacturing constrains.
> >
> >Can you suggest me some technique so i can archive this on the board.
> >
> >Board details are as fallows:
> >No. of Layers: 6
> >Stackup: top, ground, signal, signal, power, bottom
> >Board thickness is 1.6mm
> >
> >Regards,
> >S A Prasad
> >
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> >
> >----- Original Message -----
> >From: "sghsu55" <sghsu55@xxxxxxxxxxxx>
> >To: <John@xxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> >Sent: Wednesday, June 02, 2004 2:54 PM
> >Subject: [SI-LIST] Re: Power plane resonace for multi-plane issues
> >
> >
> > >
> > > John,
> > >
> > > We have ever conducted lots of simulation and
> > > measurement for the
> > > similiar PDS structure as you described. In our
> > > experiences, SpeedXP
> > > can got quite accurate results with VNA measurement.
> > > Especially, the
> > > prediction of resonance frequency of PDS plane pair.
> > > The results of
> > > SpeedXP were slightly greater than measured as well
> > > may come from the
> > > fringing effect in the edge of plane. I don't have
> > > sufficient
> > > information to understand your case and simulation
> > > setting. However,
> > > in my opinion, I don't think that the overlap between
> > > VCCP and VCC3_3
> > > is a good design.
> > >
> > > Best regards,
> > >
> > > Sogo Hsu Ph. D.
> > >
> > > Foxconn
> > >
> > >  --- John Lin (aL=A1=A6A=A1P=A1=D1) <John@xxxxxxxxxxxx>
>ao=A2XTR=A1=B1!G=
> >
> > > Dear all SI gurus,
> > > > one question regarding Power plane resonance.
> > > > Currently, I use SpeedXP from Sigrity for simulating
> > > > power plane resonance.
> > > > The set up is that
> > > >            TOP layer :       VCCP
> > > > -----  on top layer,
> > > >            2nd layer  :      GND, VCC3_3  --
> > > > partially overlap both plane  on the second layer
> > > >            3rd layer :         GND
> > > >           ....
> > > >            BOT layer:       VCCP                  --
> > > > on bottom layer
> > > >
> > > >  I inject a current pulse into VCCP at a node on the
> > > > top layer. With Fourier transfer for  voltage and
> > > > current, and got a plot of plane impedance.   My VNA
> > > > measurement shows a resonance at 50 Mhz, but the
> > > > simulation show 100Mhz.
> > > > I think the mismatch may be among , VCCP,VCC3_3, and
> > > > GND plane .  Shall I let VCC3_3 plane float or tie
> > > > it to somewhere?
> > > >
> > > > I know Cadence's PI tool need to specified each
> > > > overlapping plane pairs with correct voltage
> > > > difference for multi-plane issues.
> > > >
> > > > I don't know how to take care current injection
> > > > issues on Sigrity SpeedXP for multi-planes.
> > > >
> > > > Does somebody please kindly shed some light on it.
> > > >
> > > > Thanks,
> > > > John
> > > >
> > >
> > >
> > >
> > > -----------------------------------------------------------------
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