## [SI-LIST] Re: 50 ohm and 130 ohm on the same board

• From: msharpes@xxxxxxxxxx
• Date: Wed, 2 Jun 2004 17:00:10 -0600

```Although 130 Ohms seems on the high side, through some experience I can
talk of designing higher impedance transmission lines (in the 100 Ohm
neighborhood) for a fairly large distributed load.  So, the concept was
that the capacitive nature of each of the distributed loads served to
lower the characteristic along the line so much so in some cases that
impedances of 80-100 Ohms were desired for a 50 Ohm 'effective'
impedance.  The trick to doing this is to space the loads in an equal
pitch with the pitch being something less than an inch for the
transmission line to 'look' like something around 50 Ohms.  Now, this
isn't portable to extremely fast designs, but we have had success with
terminated transmission lines of this type with the right drive strength
and source impedance to move 2V/ns at each load in a 3.3V system.

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of steve weir
Sent: Wednesday, June 02, 2004 12:22 PM
Subject: [SI-LIST] Re: 50 ohm and 130 ohm on the same board

S A, I agree with the poster who questions the 130 ohms in the =
first=3D20
place.  Such a high impedance trace is an invitation to EMI.  That
sounds a=3D
=3D20
lot closer to the odd mode impedance for a differential pair feeding
STP=3D20
and would correspond to 65 - 75 ohms even mode depending on how tightly
you=3D
=3D20
couple. Before you go defining your board geometry, make sure your=3D20
requirements are correct.

Steve.
At 08:39 PM 6/2/2004 +0530, saprasad wrote:
>Hello All,
>
>I have a board with 2 sets of signal, the first set of nets need to be
at
>50ohm characteristic impedance and the other at 130ohm (single ended).
>This is not practically possible due to manufacturing constrains.
>
>Can you suggest me some technique so i can archive this on the board.
>
>Board details are as fallows:
>No. of Layers: 6
>Stackup: top, ground, signal, signal, power, bottom
>Board thickness is 1.6mm
>
>Regards,
>
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>----- Original Message -----
>From: "sghsu55" <sghsu55@xxxxxxxxxxxx>
>To: <John@xxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
>Sent: Wednesday, June 02, 2004 2:54 PM
>Subject: [SI-LIST] Re: Power plane resonace for multi-plane issues
>
>
> >
> > John,
> >
> > We have ever conducted lots of simulation and
> > measurement for the
> > similiar PDS structure as you described. In our
> > experiences, SpeedXP
> > can got quite accurate results with VNA measurement.
> > Especially, the
> > prediction of resonance frequency of PDS plane pair.
> > The results of
> > SpeedXP were slightly greater than measured as well
> > may come from the
> > fringing effect in the edge of plane. I don't have
> > sufficient
> > information to understand your case and simulation
> > setting. However,
> > in my opinion, I don't think that the overlap between
> > VCCP and VCC3_3
> > is a good design.
> >
> > Best regards,
> >
> > Sogo Hsu Ph. D.
> >
> > Foxconn
> >
> >  --- John Lin (aL=3DA1=3DA6A=3DA1P=3DA1=3DD1) <John@xxxxxxxxxxxx>
ao=3DA2XTR=3DA1=3DB1!G=3D
>
> > Dear all SI gurus,
> > > one question regarding Power plane resonance.
> > > Currently, I use SpeedXP from Sigrity for simulating
> > > power plane resonance.
> > > The set up is that
> > >            TOP layer :       VCCP
> > > -----  on top layer,
> > >            2nd layer  :      GND, VCC3_3  --
> > > partially overlap both plane  on the second layer
> > >            3rd layer :         GND
> > >           ....
> > >            BOT layer:       VCCP                  --
> > > on bottom layer
> > >
> > >  I inject a current pulse into VCCP at a node on the
> > > top layer. With Fourier transfer for  voltage and
> > > current, and got a plot of plane impedance.   My VNA
> > > measurement shows a resonance at 50 Mhz, but the
> > > simulation show 100Mhz.
> > > I think the mismatch may be among , VCCP,VCC3_3, and
> > > GND plane .  Shall I let VCC3_3 plane float or tie
> > > it to somewhere?
> > >
> > > I know Cadence's PI tool need to specified each
> > > overlapping plane pairs with correct voltage
> > > difference for multi-plane issues.
> > >
> > > I don't know how to take care current injection
> > > issues on Sigrity SpeedXP for multi-planes.
> > >
> > > Does somebody please kindly shed some light on it.
> > >
> > > Thanks,
> > > John
> > >
> >
> >
> >
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