[SI-LIST] Re: 12 Layer stack

My question would be:  Why not a 10 layer stackup?  Do you really think
you need 3 G/P pairs for a 133MHz part?


Aubrey Sparkman 
Enterprise Engineering Signal Integrity Team 
Dell, Inc. 
Aubrey_Sparkman@xxxxxxxx 
(512) 723-3592 
"The single biggest problem in communication is the illusion that it has
taken place." -- George Bernard Shaw



-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of wjcsongr@xxxxxxxxxxxxxxxxxxx
Sent: Monday, July 28, 2008 3:40 PM
To: Mangipudi, Prasad
Cc: 'SI LIST'; si-list-bounce@xxxxxxxxxxxxx; 'sunil bharadwaz'
Subject: [SI-LIST] Re: 12 Layer stack

All,
Another interesting topic to get the list fired up with discussion.

Prasad, please explain why you think referencing all signals to GND is a
good thing? And why coupling power planes of different noise levels in
the middle of this mess is a good thing?

Our Intel friends can certainly point to the now famous paper about this
GND referencing stuff. I believe we will discover that as always, rules
of thumb must be applied with care and not willy nilly everywhere.

I'm very interested in the comments on this one. 

I would probably vote to minimize dual stripline wiring to minimize
xtalk. 
With the stack below, you'll still have 4 good easily controlled wiring
layers, 2 on top and bottom for fan out. And you can stick a hunk of
that buried capacitance stuff in the middle. 'P' in the stack is plane.
I don't care, except in the middle, if it's power or GND. With any stack
discussed so far, you really only get 4 good layers. 

S-G-S-P-S-G-P-S-G-S-G-S.

If that dual strip doesn't bother you, go for A. 

Also, doesn't the final answer depend on how many power planes you will
need in your design? If you're a 10W board, for example, maybe one power
layer is sufficient. There's that Ohm's law thing again: - )

Regards,

Bill

William Csongradi
Senior Electrical Engineer
Rockwell Collins Heads Down Display Center
319-295-7884

Mailing Address
Rockwell Collins
400 Collins Road NE
MS 105-167
Cedar Rapids, Iowa 52498-0001





"Mangipudi, Prasad" <Prasad_Mangipudi@xxxxxxxxxxx> Sent by:
si-list-bounce@xxxxxxxxxxxxx
07/28/2008 03:19 PM

To
'sunil bharadwaz' <sunil_bharadwaz@xxxxxxxxx>, 'SI LIST' 
<si-list@xxxxxxxxxxxxx>
cc

Subject
[SI-LIST] Re: 12 Layer stack






Sunil,

Neither.  I would use S/G/S/S/G/P/P/G/S/S/G/S to simplify the design.
All signals reference to ground.  Required board thickness is achieved
by increasing the dielectric between power planes and/or signal planes.

-Prasad


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of sunil bharadwaz
Sent: Monday, July 28, 2008 11:08 AM
To: SI LIST
Subject: [SI-LIST] 12 Layer stack


Hi ,



I have following two stack up's



Stack 'A'



1)Signal

2)PWR

3)GND

4)Signal

5)PWR

6)Signal

7)Signal

8)Gnd

9)Signal

10)PWR

11)GND

12)Signal



Stack 'B'



1)Signal

2)GND

3)Signal

4)Signal

5)Ground

6)Power

7)Power

8)GND

9)Signal

10)Signal

11)PWR

12)Signal



Intent is to use one of these stacks for an FPGA based high speed Design

(Max
133 Mhz).

Can i know which one is preferable.





regards

Sunil.B






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