[SI-LIST] Re: 12 Layer stack

Sunil,

Neither.  I would use S/G/S/S/G/P/P/G/S/S/G/S to simplify the design.  All 
signals reference to ground.  Required board thickness is achieved by 
increasing the dielectric between power planes and/or signal planes.

-Prasad


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of sunil bharadwaz
Sent: Monday, July 28, 2008 11:08 AM
To: SI LIST
Subject: [SI-LIST] 12 Layer stack


Hi ,



I have following two stack up's



Stack 'A'



1)Signal

2)PWR

3)GND

4)Signal

5)PWR

6)Signal

7)Signal

8)Gnd

9)Signal

10)PWR

11)GND

12)Signal



Stack 'B'



1)Signal

2)GND

3)Signal

4)Signal

5)Ground

6)Power

7)Power

8)GND

9)Signal

10)Signal

11)PWR

12)Signal



Intent is to use one of these stacks for an FPGA based high speed Design (Max
133 Mhz).

Can i know which one is preferable.





regards

Sunil.B






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