[SI-LIST] 10G Differential routing trace width
- From: "Filion, Marc-Andre" <marc-andre.filion@xxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 14 Oct 2011 10:52:37 -0400
Hi,
I've got an easy Friday question. When it's time to design board with
multi-gigabit (> 5Gb) differential signal, we always get lost into a discussion
with CAD guys. We want more trace width to reduce loss and they want more
real-estate to fit everything. In that case, increasing dielectric thickness is
not an option because it will ruin the rest of the layer trace-2-trace
clearance. In the end, we're stuck with a 6 mils trace that will handle a 10G
signal. We know, from previous design, that it's working, but I'm not sure if
this is good practice. We have to go into 10 ~ 15 inch of routing with
interconnect.
Is there a rule of thumbs about trace width and signal speed?
When Skin effect become a problematic issue?
Many thanks,
Marc-André Filion
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