[SI-LIST] Re: 0402 capacitors and 1mm pitch BGAs

Bob,

Contrary to popular opinion, via sharing between load devices and 
decoupling capacitors is not necessarily a bad thing.   As shown in your 
photos, you will be hard pressed to do better.  But the inductance numbers 
are going to be much higher than what you saw in Lee's book, unless the 
power and ground are really close to the bottom of the stack which is bad 
for the IC.

Look at it this way using Jon's SIDRAW tool:

LINE: blue 65.0 95.0 65.0 105.0 75.0 105.0 55.0 105.0
PRIMITIVE: 0
LINE: blue 75.0 115.0 55.0 115.0 65.0 115.0 65.0 125.0
PRIMITIVE: 0
LINE: blue 65.0 125.0 65.0 145.0 75.0 155.0 85.0 145.0 75.0 135.0 65.0 
155.0 75.0 165.0 85.0 155.0 75.0 145.0 65.0 165.0 75.0 175.0 85.0 165.0 
75.0 155.0 65.0 175.0 75.0 185.0 85.0 175.0 75.0 165.0 65.0 185.0 65.0 205.0
PRIMITIVE: 2
LINE: blue 280.0 125.0 280.0 145.0 290.0 155.0 300.0 145.0 290.0 135.0 
280.0 155.0 290.0 165.0 300.0 155.0 290.0 145.0 280.0 165.0 290.0 175.0 
300.0 165.0 290.0 155.0 280.0 175.0 290.0 185.0 300.0 175.0 290.0 165.0 
280.0 185.0 280.0 205.0
PRIMITIVE: 4
LINE: blue 35.0 205.0 190.0 205.0
LINE: blue 280.0 130.0 280.0 70.0
LINE: blue 185.0 205.0 355.0 205.0
LINE: blue 120.0 95.0 120.0 115.0 130.0 125.0 140.0 115.0 130.0 105.0 120.0 
125.0 130.0 135.0 140.0 125.0 130.0 115.0 120.0 135.0 130.0 145.0 140.0 
135.0 130.0 125.0 120.0 145.0 130.0 155.0 140.0 145.0 130.0 135.0 120.0 
155.0 120.0 175.0
PRIMITIVE: 6
LINE: blue 100.0 95.0 105.0 95.0 120.0 95.0
LINE: blue 95.0 90.0 95.0 90.0
LINE: blue 95.0 95.0 60.0 95.0
LINE: blue 95.0 95.0 100.0 95.0
LINE: blue 120.0 175.0 120.0 205.0
LINE: blue 160.0 55.0 155.0 50.0 160.0 50.0
LINE: blue 220.0 95.0 220.0 115.0 230.0 125.0 240.0 115.0 230.0 105.0 220.0 
125.0 230.0 135.0 240.0 125.0 230.0 115.0 220.0 135.0 230.0 145.0 240.0 
135.0 230.0 125.0 220.0 145.0 230.0 155.0 240.0 145.0 230.0 135.0 220.0 
155.0 220.0 175.0
PRIMITIVE: 8
LINE: blue 310.0 70.0 205.0 70.0 205.0 35.0 310.0 35.0 310.0 70.0
LINE: blue 220.0 95.0 220.0 70.0
LINE: blue 220.0 170.0 220.0 230.0
LINE: blue 355.0 230.0 35.0 230.0
LINE: blue 120.0 205.0 120.0 230.0
TEXT: blue 235.0 45.0 w IC


Then just flip the capacitor and attachment inductance over and shift it to 
the right.  There is no net gain in inductance between the capacitor and 
the IC.  For centered power / ground there is a small reduction in both 
inductance and resistance, from elimination of the lateral spacing.  The 
situation gets more complex for offset planes.  Planes offset towards the 
surface definitely favor decoupling capacitors attached to the surface.

To get an economically and electrically optimized answer, you should:model 
the physical structure, or have someone do the modelling for you.  In the 
shameless plug dept.  I know people who can help.  But in the free advice 
dept. what you are doing is one of the better alternatives.

Regards,


Steve.
At 10:26 AM 4/28/2004 -0700, Bob McNamara wrote:
>Hi SI-Listers,
>
>I'm looking for feedback on producibility or other
>concerns regarding the use of 0402 capacitors with
>a 4 via footprint on a 1.0mm grid.  From measured
>data provided in Lee Ritchey's book "Right the
>First Time", this footprint yields a mounted ESL
>of about 450pH (for a via length of 13.5 mils).
>Even better, it fits the pitch of a 1mm BGA.  For
>a fully populated BGA, the only alternative
>decoupling schemes I can come up with are:
>
>1) blind vias, a good solution electrically but
>    not so great economically.
>
>2) via-in-pad, maybe the best solution
>    electrically but not so economical.
>
>3) via sharing to open up areas to place
>    capacitors.  very economical, but a definite
>    compromise electrically.
>
>For a high performance chip in a 1mm BGA package
>that requires low-inductance decoupling, dropping
>0402 capacitors in between the BGA's dispersion
>vias seems to me to be the best engineering
>choice.  Even if a higher defect rate means that 1
>of the 50 caps on an occasional board has an open
>solder joint, I'd claim that board has better
>electrical margins than a perfect board designed
>with compromised electricals to start with.
>
>What do others think?  To help visualize the cap
>and its footprint, I've uploaded a picture to:
>
>http://briefcase.yahoo.com/electronbob2@xxxxxxxxxxxxx?.dir=0402
>
>There are two resolutions: 800x600 (about 85x
>magnification assuming a 100dpi screen) and
>2032x1524 (about 220x magnification on a 100dpi
>screen).
>
>Bob
>
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