Scan design called portal for hackers

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Scan design called portal for hackers
http://www.eedesign.com/story/showArticle.jhtml?articleID=51200154

Richard Goering
EE Times
Oct 25, 2004

Santa Cruz, Calif. -- Think your "smart" credit cards are safe from
hackers, that your company firewall is secure and that no one can
steal the intellectual property in your latest chip design?

Think again. Any chip that uses scan design - and any system built
around it - may be vulnerable to hackers or to other interested third
parties, according to research that will be presented at this week's
International Test Conference in Charlotte, N.C.
(www.itctestweek.org).

There's a growing recognition in the industry that the very scan
chains that make ICs testable can potentially be used to break their
encryption algorithms and steal their intellectual property.

Opinions differ on how solvable the problem is and on what approach
provides the best possible trade-off between test and security
concerns. An ITC panel scheduled for tomorrow will air different views
on a growing dilemma: that while design-for-test methodologies aim at
making internal IC logic states visible to testers, those very same
features make chips much more vulnerable to hackers.

"Good test quality requires full access to all elements that determine
the internal state of an IC," said Erik Jan Marinessen, principal
scientist at Philips Research Labs in Eindhoven, Netherlands, and
moderator of the Tuesday panel. "Full access means full
controllability and full observability. These test requirements are in
complete contradiction to security requirements, where neither full
controllability nor observability should be given to the world
external to the IC."
snip


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