SECUR> Intel tips plans for reconfigurable radio architecture

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Intel tips plans for reconfigurable radio architecture
By Ron Wilson, EE Times
Jan 22, 2003 (11:16 AM)
URL: <http://www.commsdesign.com/story/OEG20030122S0037>

SAN JOSE, Calif. - Intel Corp. provided the first details of its
reconfigurable radio architecture this week at the Software-Defined
Radio Forum, where the company described an array of processors that
will implement a range of physical layer and media-access control combinations.

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In its first public discussion of its plans since Intel's chief
technology officer Patrick Gelsinger revealed an intent to pursue
reconfigurable radio at last year's Intel Developer Forum, Intel made
it clear that its approach will differ from most other companies at
the workshop. Rather than relying on programmable logic, Intel
researcher Jeffrey Schiffer said Monday (Jan. 20) that the company's
architecture will use a heterogeneous array of processors. Some will
be general-purpose DSPs, and others will be tuned to process
particular algorithms. Schiffer said the individual processors will
be of intermediate complexity, between an FPGA and a modest CPU.


The processors are not bused, but rather are connected through a mesh
that emphasizes nearest-neighbor relationships. This both offers a
natural implementation for data flow organizations and reduces the
power and signal integrity issues that come with long interconnect lines.

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