[minima] Re: Si5351

  • From: "Jerry Gaffke" <dmarc-noreply@xxxxxxxxxxxxx> (Redacted sender "jgaffke@xxxxxxxxx" for DMARC)
  • To: "minima@xxxxxxxxxxxxx" <minima@xxxxxxxxxxxxx>
  • Date: Thu, 6 Nov 2014 15:55:49 -0800

I had previously quoted this from an older post:

>The Si570 specs quote a phase jitter of 0.62 ps typical for the CMOS  >part.  
>The Si5351 specs quote a period jitter and cycle-to-cycle jitter  >of 50 to 70 
>ps, typical. 
Comparing apples to apples,

Page 10 of rev1.4 of the Si570 datasheet says typical pk-to-pk period jitter is 
14 ps

Page 6 of rev 0.75 of the Si5351 datasheet says to expect a typical period 
jitter of 40 to 70 ps pk-to-pk, 
depending on package and number of active outputs.
Footnote states:  "Specifications represent a worst case, real world frequency 
plan; actual performance may be substantially better"

So it may be better than I had feared.
If the output multisynth is held to integer values and only the VCO is adjusted 
using a fractional divider (SiLab's VCO control should have a low pass filter 
on it), then jitter should be considerably better than worst case.  And perhaps 
comparable to the Si570.

Note that the Si5351 has two independent VCO's, so it might be able to 
adequately drive the BFO simultaneously without resorting to a fractional 
output divider.

But looking at a handful of nice round frequencies does not fully demonstrate 
this.

Jerry







On Thursday, November 6, 2014 1:44 PM, Joe Rocci <joe@xxxxxxxxxx> wrote:
 


"Though this exciter board is wide open, a complete 
transceiver will have additional filtering as required."
 
As I commented earlier, if you're going to go to 
the effort to add front-end bandpass filtering, you'd be better off with a low 
IF architecture. Many fewer dragons to slay.
----- Original Message ----- 
>From: Jerry Gaffke (Redacted sender  "jgaffke@xxxxxxxxx" for DMARC) 
>To: minima@xxxxxxxxxxxxx 
>Sent: Thursday, November 06, 2014 4:26  PM
>Subject: [minima] Re: Si5351
>
>
>Good point, needs to be an appropriate A/B test.
>Like  40 meters with megawatt SW BC stations out in force.
>Folks  in Europe may have more stringent needs than I, way out here in the  
>boonies.
>Though  this exciter board is wide open, a complete transceiver will have 
>additional  filtering as required.Jerry
> 
>
>
>
>On Thursday, November 6, 2014 12:35 PM,  Joe Rocci <joe@xxxxxxxxxx> wrote:
>
>
>
>: 
>"And  if I can't hear the difference in a blind A/B test, it's plenty good 
>enough  for me."
>
> 
>I doubt if the noise directly impressed on the  desired receive signal would 
>be audible unless it was horrible. More of a  problem would be reciprocal 
>mixing, where a strong off-frequency signal would  be mixed back into the 
>passband as noise. This is especially problematic in  this design, where the 
>front end is wide open. A strong SW broadcast  station several Mhz away could 
>reflect back into the passband as  modulated noise. I doubt if most people 
>will have a problem with it though.  I'm sure we'll learn more soon, as this 
>part is destined to be popular. Just  as the NE602/SA612 is very popular 
>primarily for it's simplicity and ease of  use, many will be inclined make 
>allowances for compromised  performance.
> 
> 
>----- Original Message ----- 
>From: Jerry Gaffke (Redacted sender  "jgaffke@xxxxxxxxx" for DMARC) 
>>To: minima@xxxxxxxxxxxxx 
>>Sent: Thursday, November 06, 2014 2:45  PM
>>Subject: [minima] Re: Si5351
>>
>>
>>NT7S's posting says "13.371 MHz (in both fractional and  integer divider 
>>modes)". Suggests to me they used some small integer ratio  to get from 25 
>>MHz to 13.371 Mhz.  I did a quick script to look for  integer M/D's to scale 
>>25 Mhz to within 1KHz of 13.371 MHz, see quite a few  even when M and D are 
>>restricted to a max of 256.
>>
>>The  part is considerably more complicated than that, it's one (a+b/c) to  
>>determine the VCO freq, and another (a+b/c) to then scale it down for  
>>output.  Those b's and c's are 20 bits.  
>>
>>That first 
    (a+b/c) creates an error signal into the VCO, no doubt with an appropriate 
    low pass filter in the loop.  The second (a+b/c) is used to shift down 
    from the VCO to the output freq, and SiLabs recommends keeping that a clean 
    integer ratio if at all possible.  I'd guess without an integer ratio 
    on the output side (a+b/c), the output will reflect all of the choppiness 
    inherent in a fractional divide with no filtering.
>>
>>
>>You  could be right, and simply turning off "integer mode" makes it give 
>>worst  case performance.
>>I  have my doubts, though I by no means fully understand the part.
>>
>>Definitely  worth playing with.
>>
>>And  if I can't hear the difference in a blind A/B test, it's plenty good 
>>enough  for me.
>>
>>
>>
>>As  NT7S states in a reply to my comment in his blog, probably not much good 
>>for  use as a quadrature clock generator.  Phase shift is in steps of 1/4  
>>the 600-900 MHz VCO clock, and you get a maximum of 127 steps.  That  
>>restricts quadrature clocks to a minimum output frequency of around 4.724  
>>Mhz, and as the output frequency goes up the percentage error from 90  
>>degrees increases.  
>>
>>
>>
>>Jerry
>>
>>
>>
>>
>>On Thursday, November 6, 2014 10:27 AM,  Joe Rocci <joe@xxxxxxxxxx> wrote:
>>
>>
>>
>> 
>>Jerry
>> 
>>I believe one of the test frequencies on the  NT7S was some non-integer 
>>frequency around 13 Mhz. However, I seriously  doubt that changing the divide 
>>value will make any difference, as the chip  isn't being operated in the 
>>integer divide mode when using Jason's code  library, it's being operated in 
>>the fractional mode (someone correct me if  I'm wrong here). Therefore, even 
>>to get 20 MHz or most other nice even  frequencies, the a+b/c functionality 
>>is being used. What will make a noise  difference is the output frequency. As 
>>you can see from the curves, it isn't  as good at 100 Mhz as it is at 10 Mhz, 
>>nor as good as the Si570 is at 100  MHz. Still, for an under-$2 part, it's 
>>pretty compelling. Personally,  considering that the Minima's not intended to 
>>be a contest-class  rig, I think this part is very much in the 
>>low-cost/low-complexity  spirit of the rig and would be a good mod to the 
>>basic design. More  experimentation is needed here. For my part, I
 satisfied my 1st-order  level of curiosity about the part and I'm moving on. 
It is, however, now a  member in good standing in my toolbox of solutions.
>> 
>>Joe
>>W3JDR
>> 
>>----- Original Message ----- 
>>>From: Jerry Gaffke (Redacted  sender "jgaffke@xxxxxxxxx" for DMARC) 
>>>To: minima@xxxxxxxxxxxxx 
>>>Sent: Thursday, November 06, 2014  1:03 PM
>>>Subject: [minima] Re: Si5351
>>>
>>>
>>>Joe,
>>>
>>>
>>>I'm  really curious what your Si5351 noise test would show if you dialed in 
>>>a  few other frequencies at 1 Hz ticks.
>>>A  nominal freq of 20.000000 MHz from a 25 MHz crystal is easy enough for a  
>>>simple PLL with integer M/D.
>>>
>>>A  freq of 20.000001 MHz is a whole different story, as it would work  those 
>>>fractional dividers.
>>>>The Si570 specs quote a phase jitter of 0.62 ps typical for the CMOS  
>>>>>part.  The Si5351 specs quote a period jitter and cycle-to-cycle jitter  
>>>>>of 50 to 70 ps, typical. 
>>>That looks really ominous.
>>>
>>>The  Si570 VFO plus BJT xosc BFO is a fine solution.
>>>But  would be nice to know how well the cheaper Si5351 stacks up.
>>>
>>>
>>>
>>>Jerry,  KE7ER
>>>
>>>
>>>
>>>
>>>On Sat, Nov 1, 2014 at 12:15 PM, Joe Rocci <joe@xxxxxxxxxx> wrote:
Since it's a rainy Saturday afternoon here, I went down and ran another noise 
test on the Si5351 to prove to myself that the result is reproducible and to 
document the measurement with a plot (attached). You can clearly see the noise 
pedestal that's so characteristic of a 
closed-loop system. BTW, from the noise pedestal bandwidth, it appears that the 
PLL loop bandwidth is in the range of 15 khz, not as wide as I would have 
expected. The measured carrier (+6dbm after filter loss) is notched 40 db by 
the test fixture and the measured noise at +10 khz is -89dbm, well above any 
influence from the analyzer's own -105 db noise spec. The measurement bandwidth 
is 1khz, so the actual noise of the part in the typically specified 1hz BW is 
-125db/hz. If we assume that half of this noise power is due to phase noise, 
then we might say the phase noise of the part is about -128 db/hz. This is 
almost identical to what I measured for the Si570 and not much worse than my 
HP8640B signal generator, which is considered by many to be very good @ 
-135db/hz. Will this performance hold up at other frequencies? Maybe others can 
provide that answer. Maybe later today I'll do some spur plots. Joe
>>>
>
>

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