[linux-cirrus] ep93xx I2S driver
- From: Chase Douglas <cndougla@xxxxxxxxxx>
- To: linux-cirrus@xxxxxxxxxxxxx
- Date: Sun, 7 Jan 2007 15:41:49 -0500
This is a first attempt at the driver, of which I've never written
any before. I copied Lennert's AC'97 driver and tried to fit it to
the i2s stuff. For instance, I have no clue how dma stuff works, but
I hope it just works as is. I haven't written the codec chip code so
I haven't tested it yet, and I'd also like to know if my driver looks
correct before I try it. I'm going to try to not fry chips by
accident. Let me know what you all think and if I need to change
anything. This is also my first real patch I've submitted, so if I
make any faux-pas' try to flame genty...
diff --git a/arch/arm/mach-ep93xx/edb9302a.c b/arch/arm/mach-ep93xx/
edb9302a.c
index 62e064b..91031e0 100644
--- a/arch/arm/mach-ep93xx/edb9302a.c
+++ b/arch/arm/mach-ep93xx/edb9302a.c
@@ -22,6 +22,8 @@ #include <asm/io.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
+#include <sound/asound.h>
+#include <sound/control.h>
static struct physmap_flash_data edb9302a_flash_data = {
.width = 2,
@@ -69,6 +71,36 @@ static struct platform_device edb9302a_e
.resource = edb9302a_eth_resource,
};
+struct snd_kcontrol_new cs4271_controls[] = {
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = "Master Playback Volume",
+#define cs4271_volume_info NULL
+#define cs4271_volume_get NULL
+#define cs4271_volume_put NULL
+ .info = cs4271_volume_info,
+ .get = cs4271_volume_get,
+ .put = cs4271_volume_put,
+ .private_value = 0x007f0054,
+ },
+};
+
+
+static struct ep93xx_i2s_data edb9302a_i2s_data = {
+ .amp_power = NULL,
+ .codec_power = NULL,
+ .i2s_pins = I2S_ON_AC97,
+ .controls = cs4271_controls,
+};
+
+static struct platform_device edb9302a_i2s_device = {
+ .name = "ep93xx-i2s",
+ .id = -1,
+ .dev = {
+ .platform_data = &edb9302a_i2s_data,
+ },
+};
+
static void __init edb9302a_init_machine(void)
{
ep93xx_init_devices();
@@ -77,6 +109,7 @@ static void __init edb9302a_init_machine
memcpy(edb9302a_eth_data.dev_addr,
(void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
platform_device_register(&edb9302a_eth_device);
+ platform_device_register(&edb9302a_i2s_device);
}
MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
diff --git a/include/asm-arm/arch-ep93xx/ep93xx-regs.h b/include/asm-
arm/arch-ep93xx/ep93xx-regs.h
index 593f562..4346246 100644
--- a/include/asm-arm/arch-ep93xx/ep93xx-regs.h
+++ b/include/asm-arm/arch-ep93xx/ep93xx-regs.h
@@ -68,6 +68,26 @@ #define EP93XX_TIMER3_CONTROL EP93XX_TI
#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
#define EP93XX_I2S_BASE (EP93XX_APB_VIRT_BASE + 0x00020000)
+#define EP93XX_I2S_REG(x) (EP93XX_I2S_BASE + (x))
+#define EP93XX_I2S_TXCLKCFG EP93XX_I2S_REG(0x00)
+#define EP93XX_I2S_RXCLKCFG EP93XX_I2S_REG(0x04)
+#define EP93XX_I2S_GLCTRL EP93XX_I2S_REG(0x0C)
+#define EP93XX_I2S_TX0LFT EP93XX_I2S_REG(0x10)
+#define EP93XX_I2S_TX0RT EP93XX_I2S_REG(0x14)
+#define EP93XX_I2S_TX1LFT EP93XX_I2S_REG(0x18)
+#define EP93XX_I2S_TX1RT EP93XX_I2S_REG(0x1c)
+#define EP93XX_I2S_TX2LFT EP93XX_I2S_REG(0x20)
+#define EP93XX_I2S_TX2RT EP93XX_I2S_REG(0x24)
+#define EP93XX_I2S_TXLINCTRLDATA EP93XX_I2S_REG(0x28)
+#define EP93XX_I2S_TXWRDLEN EP93XX_I2S_REG(0x30)
+#define EP93XX_I2S_TX0EN EP93XX_I2S_REG(0x34)
+#define EP93XX_I2S_TX1EN EP93XX_I2S_REG(0x38)
+#define EP93XX_I2S_TX2EN EP93XX_I2S_REG(0x3C)
+#define EP93XX_I2S_RXLINCTRLDATA EP93XX_I2S_REG(0x58)
+#define EP93XX_I2S_RXWRDLEN EP93XX_I2S_REG(0x60)
+#define EP93XX_I2S_RX0EN EP93XX_I2S_REG(0x64)
+#define EP93XX_I2S_RX1EN EP93XX_I2S_REG(0x68)
+#define EP93XX_I2S_RX2EN EP93XX_I2S_REG(0x6C)
#define EP93XX_SECURITY_BASE (EP93XX_APB_VIRT_BASE + 0x00030000)
@@ -120,6 +140,7 @@ #define EP93XX_SYSCON_CLOCK_SET1 EP93XX_
#define EP93XX_SYSCON_CLOCK_SET2 EP93XX_SYSCON_REG(0x24)
#define EP93XX_SYSCON_DEVICE_CONFIG EP93XX_SYSCON_REG(0x80)
#define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE 0x00800000
+#define EP93XX_SYSCON_I2SDIV EP93XX_SYSCON_REG(0x8c)
#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
#define EP93XX_WATCHDOG_BASE (EP93XX_APB_VIRT_BASE + 0x00140000)
diff --git a/include/asm-arm/arch-ep93xx/platform.h b/include/asm-arm/
arch-ep93xx/platform.h
index b4a8deb..863a408 100644
--- a/include/asm-arm/arch-ep93xx/platform.h
+++ b/include/asm-arm/arch-ep93xx/platform.h
@@ -4,6 +4,9 @@
#ifndef __ASSEMBLY__
+#define I2S_ON_AC97 1
+#define I2S_ON_SSP 0
+
void ep93xx_map_io(void);
void ep93xx_init_irq(void);
void ep93xx_init_time(unsigned long);
@@ -11,6 +14,20 @@ void ep93xx_init_devices(void);
void ep93xx_clock_init(void);
extern struct sys_timer ep93xx_timer;
+struct ep93xx_ac97_audio_ops
+{
+ void (*amp_power)(int on);
+ void (*codec_power)(int on);
+};
+
+struct ep93xx_i2s_data
+{
+ void (*amp_power)(int on);
+ void (*codec_power)(int on);
+ char i2s_pins;
+ struct snd_kcontrol_new *controls;
+};
+
struct ep93xx_eth_data
{
unsigned char dev_addr[6];
diff --git a/sound/arm/Kconfig b/sound/arm/Kconfig
index 2e4a5e0..97ccbf1 100644
--- a/sound/arm/Kconfig
+++ b/sound/arm/Kconfig
@@ -33,6 +33,14 @@ help
Say Y or M if you want to support any AC97 codec attached to
the EP93xx AC97 interface.
+config SND_EP93XX_I2S
+ tristate "I2S driver for the Cirrus EP93xx chip"
+ depends on ARCH_EP93XX && SND
+ select SND_EP93XX_PCM
+ help
+ Say Y or M if you want to support any I2S codec attached to
+ the EP93xx I2S interface.
+
config SND_PXA2XX_PCM
tristate
select SND_PCM
diff --git a/sound/arm/Makefile b/sound/arm/Makefile
index 4ef6dd0..c125790 100644
--- a/sound/arm/Makefile
+++ b/sound/arm/Makefile
@@ -14,6 +14,9 @@
obj-$(CONFIG_SND_EP93XX_AC97) += snd-ep93xx-ac97.o
snd-ep93xx-ac97-objs := ep93xx-ac97.o
+obj-$(CONFIG_SND_EP93XX_I2S) += snd-ep93xx-i2s.o
+snd-ep93xx-i2s-objs := ep93xx-i2s.o
+
obj-$(CONFIG_SND_PXA2XX_PCM) += snd-pxa2xx-pcm.o
snd-pxa2xx-pcm-objs := pxa2xx-pcm.o
diff --git a/sound/arm/ep93xx-i2s.c b/sound/arm/ep93xx-i2s.c
new file mode 100644
index 0000000..bd6facf
--- /dev/null
+++ b/sound/arm/ep93xx-i2s.c
@@ -0,0 +1,336 @@
+/*
+ * linux/sound/arm/ep93xx-i2s.c - EP93xx I2S driver
+ *
+ * Copyright (C) 2007 Chase Douglas <chasedouglas at gmail>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/wait.h>
+#include <linux/delay.h>
+#include <sound/driver.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/initval.h>
+#include <sound/control.h>
+#include <asm/irq.h>
+#include <linux/mutex.h>
+#include <asm/hardware.h>
+#include <asm/arch/ep93xx-regs.h>
+#include <asm/arch/dma.h>
+#include "ep93xx-pcm.h"
+#include "ep93xx-i2s.h"
+
+#define AUDIO_SAMPLE_RATE_DEFAULT 44100
+
+#define locked_writel(x,y) \
+ writel(0xaa, EP93XX_SYSCON_SWLOCK); \
+ writel((x), (y));
+
+void ep93xx_set_samplerate(long frequency);
+
+/* I2S PCM handling
*********************************************************/
+static struct ep93xx_pcm_dma_params ep93xx_i2s_pcm_out = {
+ .name = "I2S PCM out",
+ .dma_port = EP93XX_DMA_M2P_PORT_I2S1,
+};
+
+static struct ep93xx_pcm_dma_params ep93xx_i2s_pcm_in = {
+ .name = "I2S PCM in",
+ .dma_port = EP93XX_DMA_M2P_PORT_I2S1,
+};
+
+static struct snd_pcm *ep93xx_i2s_pcm;
+
+static int ep93xx_i2s_pcm_startup(struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct ep93xx_i2s_data *data;
+
+ runtime->hw.channels_min = 2;
+ runtime->hw.channels_max = 2;
+
+ runtime->hw.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |
+ SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |
+ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
+ SNDRV_PCM_RATE_48000;
+
+ snd_pcm_limit_hw_rates(runtime);
+
+ data = substream->pcm->card->dev->platform_data;
+ if (data != NULL && data->amp_power != NULL)
+ data->amp_power(1);
+
+ return 0;
+}
+
+static void ep93xx_i2s_pcm_shutdown(struct snd_pcm_substream
*substream)
+{
+ struct ep93xx_i2s_data *data;
+
+ data = substream->pcm->card->dev->platform_data;
+ if (data != NULL && data->amp_power != NULL)
+ data->amp_power(0);
+}
+
+static int ep93xx_i2s_pcm_prepare(struct snd_pcm_substream *substream)
+{
+ ep93xx_set_samplerate(substream->runtime->rate);
+ return 0;
+}
+
+static struct ep93xx_pcm_client ep93xx_i2s_pcm_client = {
+ .playback_params = &ep93xx_i2s_pcm_out,
+ .capture_params = &ep93xx_i2s_pcm_in,
+ .startup = ep93xx_i2s_pcm_startup,
+ .shutdown = ep93xx_i2s_pcm_shutdown,
+ .prepare = ep93xx_i2s_pcm_prepare,
+};
+
+/* I2S Clock Generation (From Cirrus Linux)
********************************/
+static unsigned long ep93xx_get_pll_frequency(unsigned long clkset)
+{
+ unsigned long x1fbd, x2fbd, x2ipd, ps, pll_freq;;
+
+ ps = (clkset & SYSCON_CLKSET1_PLL1_PS_MASK) >>
SYSCON_CLKSET1_PLL1_PS_SHIFT;
+ x1fbd = (clkset & SYSCON_CLKSET1_PLL1_X1FBD1_MASK) >>
SYSCON_CLKSET1_PLL1_X1FBD1_SHIFT;
+ x2fbd = (clkset & SYSCON_CLKSET1_PLL1_X2FBD2_MASK) >>
SYSCON_CLKSET1_PLL1_X2FBD2_SHIFT;
+ x2ipd = (clkset & SYSCON_CLKSET1_PLL1_X2IPD_MASK) >>
SYSCON_CLKSET1_PLL1_X2IPD_SHIFT;
+
+ pll_freq = (((0x00e10000 * (x1fbd + 1)) / (x2ipd + 1)) *
(x2fbd + 1)) >> ps;
+
+ return pll_freq;
+}
+
+static int ep93xx_calc_closest_freq(unsigned long pll_freq, unsigned
long requested_mclk_freq, unsigned long * actual_mclk_freq, unsigned
long * i2sdiv)
+{
+ unsigned long lower;
+ unsigned long upper;
+ unsigned long div;
+ int x;
+
+ div = (pll_freq * 2)/ requested_mclk_freq;
+
+ for(x = 1; x < ARRAY_SIZE(i2sdiv_table); x++)
+ {
+ lower = i2sdiv_table[x - 1].total_div;
+ upper = i2sdiv_table[x].total_div;
+
+ if(lower <= div && div < upper)
+ {
+ break;
+ }
+ }
+
+ if(x == ARRAY_SIZE(i2sdiv_table))
+ {
+ *actual_mclk_freq = 0;
+ *i2sdiv = 0;
+ return -1;
+ }
+
+ if(upper * requested_mclk_freq - pll_freq * 2 >
+ pll_freq * 2 - lower * requested_mclk_freq)
+ {
+ x -= 1;
+ }
+ *actual_mclk_freq = (pll_freq * 2)/ i2sdiv_table[x].total_div;
+ *i2sdiv = i2sdiv_table[x].i2sdiv;
+
+ return 0;
+}
+
+void ep93xx_set_samplerate(long frequency)
+{
+ unsigned long requested_mclk_freq, pll1_clock, pll2_clock;
+ unsigned long mclk_freq1, mclk_freq2, clkset1, clkset2;
+ unsigned long i2sdiv1, i2sdiv2, i2sdiv, actual_samplerate;
+ unsigned long m2s_clock = 4;
+ unsigned long s2lr_clock = 64;
+
+ clkset1 = readl(EP93XX_SYSCON_CLOCK_SET1);
+ clkset2 = readl(EP93XX_SYSCON_CLOCK_SET2);
+ pll1_clock = ep93xx_get_pll_frequency( clkset1 );
+ pll2_clock = ep93xx_get_pll_frequency( clkset2 );
+
+ requested_mclk_freq = ( frequency * m2s_clock * s2lr_clock);
+
+ ep93xx_calc_closest_freq(pll1_clock, requested_mclk_freq,
&mclk_freq1, &i2sdiv1);
+ ep93xx_calc_closest_freq(pll2_clock, requested_mclk_freq,
&mclk_freq2, &i2sdiv2);
+
+ if(abs(mclk_freq1 - requested_mclk_freq) < abs(mclk_freq2 -
requested_mclk_freq))
+ {
+ i2sdiv = i2sdiv1;
+ actual_samplerate = mclk_freq1/ (m2s_clock *
s2lr_clock);
+ }
+ else
+ {
+ i2sdiv = i2sdiv2 | SYSCON_I2SDIV_PSEL;
+ actual_samplerate = mclk_freq1 / (m2s_clock *
s2lr_clock);
+ }
+
+ i2sdiv = i2sdiv | SYSCON_I2SDIV_SENA | SYSCON_I2SDIV_ORIDE |
+ SYSCON_I2SDIV_SPOL|
SYSCON_I2SDIV_LRDIV_64 |
+ SYSCON_I2SDIV_SDIV |
SYSCON_I2SDIV_MENA | SYSCON_I2SDIV_ESEL;
+
+ locked_writel(i2sdiv, EP93XX_SYSCON_I2SDIV);
+}
+
+/* I2S platform driver
****************************************************/
+static int ep93xx_i2s_probe(struct platform_device *dev)
+{
+ struct ep93xx_i2s_data *dev_data = dev->dev.platform_data;
+ struct snd_card *card;
+ int ret;
+ int i;
+ unsigned int dev_cfg;
+
+ printk(KERN_INFO "ep93xx-i2s: resetting i2s controller\n");
+ writel(0, EP93XX_I2S_TX0EN);
+ writel(0, EP93XX_I2S_TX1EN);
+ writel(0, EP93XX_I2S_TX2EN);
+ writel(0, EP93XX_I2S_RX0EN);
+ writel(0, EP93XX_I2S_RX1EN);
+ writel(0, EP93XX_I2S_RX2EN);
+ writel(0, EP93XX_I2S_GLCTRL);
+
+ ep93xx_set_samplerate(AUDIO_SAMPLE_RATE_DEFAULT);
+
+ dev_cfg = readl(EP93XX_SYSCON_DEVICE_CONFIG);
+ dev_cfg |= (dev_data->i2s_pins == I2S_ON_AC97 ?
SYSCON_DEVICE_CONFIG_I2S_ON_AC97 : SYSCON_DEVICE_CONFIG_I2S_ON_SSP);
+ locked_writel(dev_cfg, EP93XX_SYSCON_DEVICE_CONFIG);
+
+ writel(0, EP93XX_I2S_TXLINCTRLDATA);
+ writel(1, EP93XX_I2S_TXWRDLEN);
+ writel(0xc, EP93XX_I2S_TXCLKCFG);
+ writel(0, EP93XX_I2S_RXLINCTRLDATA);
+ writel(1, EP93XX_I2S_RXWRDLEN);
+ writel(0x5c, EP93XX_I2S_RXCLKCFG);
+
+ writel(1, EP93XX_I2S_GLCTRL);
+
+ for (i = 0; i < 8; i++) {
+ writel(0, EP93XX_I2S_TX0LFT);
+ writel(0, EP93XX_I2S_TX0RT);
+ writel(0, EP93XX_I2S_TX1LFT);
+ writel(0, EP93XX_I2S_TX1RT);
+ writel(0, EP93XX_I2S_TX2LFT);
+ writel(0, EP93XX_I2S_TX2RT);
+ }
+
+ writel(1, EP93XX_I2S_TX0EN);
+ writel(1, EP93XX_I2S_TX1EN);
+ writel(1, EP93XX_I2S_TX2EN);
+ writel(1, EP93XX_I2S_RX0EN);
+ writel(1, EP93XX_I2S_RX1EN);
+ writel(1, EP93XX_I2S_RX2EN);
+
+ if (dev_data != NULL && dev_data->codec_power != NULL) {
+ dev_data->codec_power(1);
+ msleep(1);
+ }
+
+ card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
+ THIS_MODULE, 0);
+ if (card == NULL) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ card->dev = &dev->dev;
+ strncpy(card->driver, dev->dev.driver->name, sizeof(card->driver));
+
+ ret = ep93xx_pcm_new(card, &ep93xx_i2s_pcm_client, &ep93xx_i2s_pcm);
+ if (ret)
+ goto err;
+
+ for (i = 0; i < ARRAY_SIZE(dev_data->controls); i++) {
+ if (snd_ctl_add(card, snd_ctl_new1(&dev_data->controls[i], NULL))
< 0) {
+ goto err;
+ }
+ }
+ strcpy(card->mixername, "EP93XX I2S MIXER");
+
+ snprintf(card->shortname, sizeof(card->shortname),
+ "%s", "ep93xx i2s audio");
+ snprintf(card->longname, sizeof(card->longname),
+ "%s (%s)", dev->dev.driver->name, card->mixername);
+
+ ret = snd_card_register(card);
+ if (ret)
+ goto err;
+
+ platform_set_drvdata(dev, card);
+
+ return 0;
+
+err:
+ /* @@@ This causes hangs..
+ * if (card != NULL)
+ * snd_card_free(card);
+ */
+
+ return ret;
+}
+
+static int ep93xx_i2s_remove(struct platform_device *dev)
+{
+ struct snd_card *card = platform_get_drvdata(dev);
+
+ if (card != NULL) {
+ snd_card_free(card);
+ platform_set_drvdata(dev, NULL);
+ writel(0, EP93XX_I2S_GLCTRL);
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int ep93xx_i2s_suspend(struct platform_device *dev,
pm_message_t state)
+{
+ return 0;
+}
+
+static int ep93xx_i2s_resume(struct platform_device *dev)
+{
+ return 0;
+}
+#else
+#define ep93xx_i2s_suspend NULL
+#define ep93xx_i2s_resume NULL
+#endif
+
+static struct platform_driver ep93xx_i2s_driver = {
+ .probe = ep93xx_i2s_probe,
+ .remove = ep93xx_i2s_remove,
+ .suspend = ep93xx_i2s_suspend,
+ .resume = ep93xx_i2s_resume,
+ .driver = {
+ .name = "ep93xx-i2s",
+ },
+};
+
+static int __init ep93xx_i2s_init(void)
+{
+ return platform_driver_register(&ep93xx_i2s_driver);
+}
+
+static void __exit ep93xx_i2s_exit(void)
+{
+ platform_driver_unregister(&ep93xx_i2s_driver);
+}
+
+module_init(ep93xx_i2s_init);
+module_exit(ep93xx_i2s_exit);
+
+MODULE_AUTHOR("Chase Douglas <chasedouglas at gmail>");
+MODULE_DESCRIPTION("EP93xx I2S driver");
+MODULE_LICENSE("GPL");
diff --git a/sound/arm/ep93xx-i2s.h b/sound/arm/ep93xx-i2s.h
new file mode 100644
index 0000000..b4ed063
--- /dev/null
+++ b/sound/arm/ep93xx-i2s.h
@@ -0,0 +1,347 @@
+/*
+ * linux/sound/arm/ep93xx-i2s.c - EP93xx I2S driver
+ *
+ * Copyright (C) 2006 Lennert Buytenhek <buytenh at wantstofly.org>
+ * Copyright (C) 2006 Applied Data Systems
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define SYSCON_I2SDIV_SENA 0x80000000
+#define SYSCON_I2SDIV_SLAVE 0x40000000
+#define SYSCON_I2SDIV_ORIDE 0x20000000
+#define SYSCON_I2SDIV_DROP 0x00100000
+#define SYSCON_I2SDIV_SPOL 0x00080000
+#define SYSCON_I2SDIV_lRDIV_128 0x00040000
+#define SYSCON_I2SDIV_LRDIV_64 0x00020000
+#define SYSCON_I2SDIV_LRDIV_32 0x00000000
+#define SYSCON_I2SDIV_SDIV 0x00010000
+#define SYSCON_I2SDIV_MENA 0x00008000
+#define SYSCON_I2SDIV_ESEL 0x00004000
+#define SYSCON_I2SDIV_PSEL 0x00002000
+#define SYSCON_I2SDIV_PDIV_2 0x00000100
+#define SYSCON_I2SDIV_PDIV_25 0x00000200
+#define SYSCON_I2SDIV_PDIV_3 0x00000300
+#define SYSCON_I2SDIV_MDIV_MASK 0x0000007f
+
+#define SYSCON_CLKSET1_PLL1_PS_MASK 0x00030000
+#define SYSCON_CLKSET1_PLL1_PS_SHIFT 16
+#define SYSCON_CLKSET1_PLL1_X1FBD1_MASK 0x0000f800
+#define SYSCON_CLKSET1_PLL1_X1FBD1_SHIFT 11
+#define SYSCON_CLKSET1_PLL1_X2FBD2_MASK 0x000007e0
+#define SYSCON_CLKSET1_PLL1_X2FBD2_SHIFT 5
+#define SYSCON_CLKSET1_PLL1_X2IPD_MASK 0x0000001f
+#define SYSCON_CLKSET1_PLL1_X2IPD_SHIFT 0
+
+#define SYSCON_DEVICE_CONFIG_I2S_ON_SSP 0x00000080
+#define SYSCON_DEVICE_CONFIG_I2S_ON_AC97 0x00000040
+
+typedef struct {
+ unsigned long total_div;
+ unsigned long i2sdiv;
+} div_table;
+
+static const div_table i2sdiv_table[] =
+{
+ { 6, SYSCON_I2SDIV_PDIV_2 | ( 2 &
SYSCON_I2SDIV_MDIV_MASK) }, /* Fake entry for lower limit. */
+ { 8, SYSCON_I2SDIV_PDIV_2 | ( 2 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 10, SYSCON_I2SDIV_PDIV_25 | ( 2 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 12, SYSCON_I2SDIV_PDIV_3 | ( 2 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 15, SYSCON_I2SDIV_PDIV_25 | ( 3 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 16, SYSCON_I2SDIV_PDIV_2 | ( 4 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 18, SYSCON_I2SDIV_PDIV_3 | ( 3 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 20, SYSCON_I2SDIV_PDIV_25 | ( 4 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 24, SYSCON_I2SDIV_PDIV_3 | ( 4 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 25, SYSCON_I2SDIV_PDIV_25 | ( 5 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 28, SYSCON_I2SDIV_PDIV_2 | ( 7 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 30, SYSCON_I2SDIV_PDIV_3 | ( 5 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 32, SYSCON_I2SDIV_PDIV_2 | ( 8 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 35, SYSCON_I2SDIV_PDIV_25 | ( 7 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 36, SYSCON_I2SDIV_PDIV_3 | ( 6 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 40, SYSCON_I2SDIV_PDIV_25 | ( 8 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 42, SYSCON_I2SDIV_PDIV_3 | ( 7 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 44, SYSCON_I2SDIV_PDIV_2 | ( 11 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 45, SYSCON_I2SDIV_PDIV_25 | ( 9 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 48, SYSCON_I2SDIV_PDIV_3 | ( 8 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 50, SYSCON_I2SDIV_PDIV_25 | ( 10 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 52, SYSCON_I2SDIV_PDIV_2 | ( 13 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 54, SYSCON_I2SDIV_PDIV_3 | ( 9 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 55, SYSCON_I2SDIV_PDIV_25 | ( 11 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 56, SYSCON_I2SDIV_PDIV_2 | ( 14 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 60, SYSCON_I2SDIV_PDIV_3 | ( 10 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 64, SYSCON_I2SDIV_PDIV_2 | ( 16 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 65, SYSCON_I2SDIV_PDIV_25 | ( 13 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 66, SYSCON_I2SDIV_PDIV_3 | ( 11 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 68, SYSCON_I2SDIV_PDIV_2 | ( 17 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 70, SYSCON_I2SDIV_PDIV_25 | ( 14 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 72, SYSCON_I2SDIV_PDIV_3 | ( 12 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 75, SYSCON_I2SDIV_PDIV_25 | ( 15 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 76, SYSCON_I2SDIV_PDIV_2 | ( 19 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 78, SYSCON_I2SDIV_PDIV_3 | ( 13 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 80, SYSCON_I2SDIV_PDIV_25 | ( 16 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 84, SYSCON_I2SDIV_PDIV_3 | ( 14 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 85, SYSCON_I2SDIV_PDIV_25 | ( 17 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 88, SYSCON_I2SDIV_PDIV_2 | ( 22 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 90, SYSCON_I2SDIV_PDIV_3 | ( 15 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 92, SYSCON_I2SDIV_PDIV_2 | ( 23 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 95, SYSCON_I2SDIV_PDIV_25 | ( 19 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 96, SYSCON_I2SDIV_PDIV_3 | ( 16 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 100, SYSCON_I2SDIV_PDIV_25 | ( 20 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 102, SYSCON_I2SDIV_PDIV_3 | ( 17 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 104, SYSCON_I2SDIV_PDIV_2 | ( 26 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 105, SYSCON_I2SDIV_PDIV_25 | ( 21 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 108, SYSCON_I2SDIV_PDIV_3 | ( 18 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 110, SYSCON_I2SDIV_PDIV_25 | ( 22 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 112, SYSCON_I2SDIV_PDIV_2 | ( 28 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 114, SYSCON_I2SDIV_PDIV_3 | ( 19 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 115, SYSCON_I2SDIV_PDIV_25 | ( 23 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 116, SYSCON_I2SDIV_PDIV_2 | ( 29 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 120, SYSCON_I2SDIV_PDIV_3 | ( 20 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 124, SYSCON_I2SDIV_PDIV_2 | ( 31 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 125, SYSCON_I2SDIV_PDIV_25 | ( 25 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 126, SYSCON_I2SDIV_PDIV_3 | ( 21 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 128, SYSCON_I2SDIV_PDIV_2 | ( 32 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 130, SYSCON_I2SDIV_PDIV_25 | ( 26 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 132, SYSCON_I2SDIV_PDIV_3 | ( 22 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 135, SYSCON_I2SDIV_PDIV_25 | ( 27 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 136, SYSCON_I2SDIV_PDIV_2 | ( 34 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 138, SYSCON_I2SDIV_PDIV_3 | ( 23 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 140, SYSCON_I2SDIV_PDIV_25 | ( 28 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 144, SYSCON_I2SDIV_PDIV_3 | ( 24 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 145, SYSCON_I2SDIV_PDIV_25 | ( 29 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 148, SYSCON_I2SDIV_PDIV_2 | ( 37 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 150, SYSCON_I2SDIV_PDIV_3 | ( 25 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 152, SYSCON_I2SDIV_PDIV_2 | ( 38 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 155, SYSCON_I2SDIV_PDIV_25 | ( 31 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 156, SYSCON_I2SDIV_PDIV_3 | ( 26 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 160, SYSCON_I2SDIV_PDIV_25 | ( 32 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 162, SYSCON_I2SDIV_PDIV_3 | ( 27 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 164, SYSCON_I2SDIV_PDIV_2 | ( 41 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 165, SYSCON_I2SDIV_PDIV_25 | ( 33 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 168, SYSCON_I2SDIV_PDIV_3 | ( 28 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 170, SYSCON_I2SDIV_PDIV_25 | ( 34 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 172, SYSCON_I2SDIV_PDIV_2 | ( 43 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 174, SYSCON_I2SDIV_PDIV_3 | ( 29 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 175, SYSCON_I2SDIV_PDIV_25 | ( 35 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 176, SYSCON_I2SDIV_PDIV_2 | ( 44 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 180, SYSCON_I2SDIV_PDIV_3 | ( 30 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 184, SYSCON_I2SDIV_PDIV_2 | ( 46 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 185, SYSCON_I2SDIV_PDIV_25 | ( 37 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 186, SYSCON_I2SDIV_PDIV_3 | ( 31 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 188, SYSCON_I2SDIV_PDIV_2 | ( 47 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 190, SYSCON_I2SDIV_PDIV_25 | ( 38 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 192, SYSCON_I2SDIV_PDIV_3 | ( 32 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 195, SYSCON_I2SDIV_PDIV_25 | ( 39 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 196, SYSCON_I2SDIV_PDIV_2 | ( 49 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 198, SYSCON_I2SDIV_PDIV_3 | ( 33 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 200, SYSCON_I2SDIV_PDIV_25 | ( 40 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 204, SYSCON_I2SDIV_PDIV_3 | ( 34 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 205, SYSCON_I2SDIV_PDIV_25 | ( 41 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 208, SYSCON_I2SDIV_PDIV_2 | ( 52 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 210, SYSCON_I2SDIV_PDIV_3 | ( 35 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 212, SYSCON_I2SDIV_PDIV_2 | ( 53 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 215, SYSCON_I2SDIV_PDIV_25 | ( 43 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 216, SYSCON_I2SDIV_PDIV_3 | ( 36 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 220, SYSCON_I2SDIV_PDIV_25 | ( 44 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 222, SYSCON_I2SDIV_PDIV_3 | ( 37 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 224, SYSCON_I2SDIV_PDIV_2 | ( 56 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 225, SYSCON_I2SDIV_PDIV_25 | ( 45 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 228, SYSCON_I2SDIV_PDIV_3 | ( 38 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 230, SYSCON_I2SDIV_PDIV_25 | ( 46 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 232, SYSCON_I2SDIV_PDIV_2 | ( 58 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 234, SYSCON_I2SDIV_PDIV_3 | ( 39 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 235, SYSCON_I2SDIV_PDIV_25 | ( 47 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 236, SYSCON_I2SDIV_PDIV_2 | ( 59 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 240, SYSCON_I2SDIV_PDIV_3 | ( 40 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 244, SYSCON_I2SDIV_PDIV_2 | ( 61 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 245, SYSCON_I2SDIV_PDIV_25 | ( 49 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 246, SYSCON_I2SDIV_PDIV_3 | ( 41 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 248, SYSCON_I2SDIV_PDIV_2 | ( 62 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 250, SYSCON_I2SDIV_PDIV_25 | ( 50 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 252, SYSCON_I2SDIV_PDIV_3 | ( 42 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 255, SYSCON_I2SDIV_PDIV_25 | ( 51 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 256, SYSCON_I2SDIV_PDIV_2 | ( 64 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 258, SYSCON_I2SDIV_PDIV_3 | ( 43 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 260, SYSCON_I2SDIV_PDIV_25 | ( 52 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 264, SYSCON_I2SDIV_PDIV_3 | ( 44 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 265, SYSCON_I2SDIV_PDIV_25 | ( 53 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 268, SYSCON_I2SDIV_PDIV_2 | ( 67 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 270, SYSCON_I2SDIV_PDIV_3 | ( 45 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 272, SYSCON_I2SDIV_PDIV_2 | ( 68 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 275, SYSCON_I2SDIV_PDIV_25 | ( 55 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 276, SYSCON_I2SDIV_PDIV_3 | ( 46 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 280, SYSCON_I2SDIV_PDIV_25 | ( 56 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 282, SYSCON_I2SDIV_PDIV_3 | ( 47 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 284, SYSCON_I2SDIV_PDIV_2 | ( 71 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 285, SYSCON_I2SDIV_PDIV_25 | ( 57 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 288, SYSCON_I2SDIV_PDIV_3 | ( 48 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 290, SYSCON_I2SDIV_PDIV_25 | ( 58 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 292, SYSCON_I2SDIV_PDIV_2 | ( 73 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 294, SYSCON_I2SDIV_PDIV_3 | ( 49 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 295, SYSCON_I2SDIV_PDIV_25 | ( 59 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 296, SYSCON_I2SDIV_PDIV_2 | ( 74 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 300, SYSCON_I2SDIV_PDIV_3 | ( 50 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 304, SYSCON_I2SDIV_PDIV_2 | ( 76 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 305, SYSCON_I2SDIV_PDIV_25 | ( 61 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 306, SYSCON_I2SDIV_PDIV_3 | ( 51 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 308, SYSCON_I2SDIV_PDIV_2 | ( 77 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 310, SYSCON_I2SDIV_PDIV_25 | ( 62 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 312, SYSCON_I2SDIV_PDIV_3 | ( 52 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 315, SYSCON_I2SDIV_PDIV_25 | ( 63 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 316, SYSCON_I2SDIV_PDIV_2 | ( 79 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 318, SYSCON_I2SDIV_PDIV_3 | ( 53 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 320, SYSCON_I2SDIV_PDIV_25 | ( 64 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 324, SYSCON_I2SDIV_PDIV_3 | ( 54 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 325, SYSCON_I2SDIV_PDIV_25 | ( 65 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 328, SYSCON_I2SDIV_PDIV_2 | ( 82 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 330, SYSCON_I2SDIV_PDIV_3 | ( 55 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 332, SYSCON_I2SDIV_PDIV_2 | ( 83 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 335, SYSCON_I2SDIV_PDIV_25 | ( 67 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 336, SYSCON_I2SDIV_PDIV_3 | ( 56 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 340, SYSCON_I2SDIV_PDIV_25 | ( 68 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 342, SYSCON_I2SDIV_PDIV_3 | ( 57 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 344, SYSCON_I2SDIV_PDIV_2 | ( 86 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 345, SYSCON_I2SDIV_PDIV_25 | ( 69 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 348, SYSCON_I2SDIV_PDIV_3 | ( 58 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 350, SYSCON_I2SDIV_PDIV_25 | ( 70 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 352, SYSCON_I2SDIV_PDIV_2 | ( 88 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 354, SYSCON_I2SDIV_PDIV_3 | ( 59 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 355, SYSCON_I2SDIV_PDIV_25 | ( 71 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 356, SYSCON_I2SDIV_PDIV_2 | ( 89 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 360, SYSCON_I2SDIV_PDIV_3 | ( 60 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 364, SYSCON_I2SDIV_PDIV_2 | ( 91 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 365, SYSCON_I2SDIV_PDIV_25 | ( 73 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 366, SYSCON_I2SDIV_PDIV_3 | ( 61 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 368, SYSCON_I2SDIV_PDIV_2 | ( 92 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 370, SYSCON_I2SDIV_PDIV_25 | ( 74 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 372, SYSCON_I2SDIV_PDIV_3 | ( 62 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 375, SYSCON_I2SDIV_PDIV_25 | ( 75 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 376, SYSCON_I2SDIV_PDIV_2 | ( 94 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 378, SYSCON_I2SDIV_PDIV_3 | ( 63 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 380, SYSCON_I2SDIV_PDIV_25 | ( 76 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 384, SYSCON_I2SDIV_PDIV_3 | ( 64 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 385, SYSCON_I2SDIV_PDIV_25 | ( 77 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 388, SYSCON_I2SDIV_PDIV_2 | ( 97 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 390, SYSCON_I2SDIV_PDIV_3 | ( 65 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 392, SYSCON_I2SDIV_PDIV_2 | ( 98 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 395, SYSCON_I2SDIV_PDIV_25 | ( 79 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 396, SYSCON_I2SDIV_PDIV_3 | ( 66 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 400, SYSCON_I2SDIV_PDIV_25 | ( 80 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 402, SYSCON_I2SDIV_PDIV_3 | ( 67 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 404, SYSCON_I2SDIV_PDIV_2 | (101 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 405, SYSCON_I2SDIV_PDIV_25 | ( 81 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 408, SYSCON_I2SDIV_PDIV_3 | ( 68 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 410, SYSCON_I2SDIV_PDIV_25 | ( 82 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 412, SYSCON_I2SDIV_PDIV_2 | (103 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 414, SYSCON_I2SDIV_PDIV_3 | ( 69 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 415, SYSCON_I2SDIV_PDIV_25 | ( 83 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 416, SYSCON_I2SDIV_PDIV_2 | (104 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 420, SYSCON_I2SDIV_PDIV_3 | ( 70 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 424, SYSCON_I2SDIV_PDIV_2 | (106 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 425, SYSCON_I2SDIV_PDIV_25 | ( 85 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 426, SYSCON_I2SDIV_PDIV_3 | ( 71 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 428, SYSCON_I2SDIV_PDIV_2 | (107 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 430, SYSCON_I2SDIV_PDIV_25 | ( 86 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 432, SYSCON_I2SDIV_PDIV_3 | ( 72 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 435, SYSCON_I2SDIV_PDIV_25 | ( 87 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 436, SYSCON_I2SDIV_PDIV_2 | (109 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 438, SYSCON_I2SDIV_PDIV_3 | ( 73 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 440, SYSCON_I2SDIV_PDIV_25 | ( 88 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 444, SYSCON_I2SDIV_PDIV_3 | ( 74 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 445, SYSCON_I2SDIV_PDIV_25 | ( 89 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 448, SYSCON_I2SDIV_PDIV_2 | (112 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 450, SYSCON_I2SDIV_PDIV_3 | ( 75 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 452, SYSCON_I2SDIV_PDIV_2 | (113 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 455, SYSCON_I2SDIV_PDIV_25 | ( 91 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 456, SYSCON_I2SDIV_PDIV_3 | ( 76 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 460, SYSCON_I2SDIV_PDIV_25 | ( 92 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 462, SYSCON_I2SDIV_PDIV_3 | ( 77 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 464, SYSCON_I2SDIV_PDIV_2 | (116 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 465, SYSCON_I2SDIV_PDIV_25 | ( 93 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 468, SYSCON_I2SDIV_PDIV_3 | ( 78 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 470, SYSCON_I2SDIV_PDIV_25 | ( 94 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 472, SYSCON_I2SDIV_PDIV_2 | (118 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 474, SYSCON_I2SDIV_PDIV_3 | ( 79 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 475, SYSCON_I2SDIV_PDIV_25 | ( 95 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 476, SYSCON_I2SDIV_PDIV_2 | (119 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 480, SYSCON_I2SDIV_PDIV_3 | ( 80 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 484, SYSCON_I2SDIV_PDIV_2 | (121 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 485, SYSCON_I2SDIV_PDIV_25 | ( 97 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 486, SYSCON_I2SDIV_PDIV_3 | ( 81 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 488, SYSCON_I2SDIV_PDIV_2 | (122 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 490, SYSCON_I2SDIV_PDIV_25 | ( 98 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 492, SYSCON_I2SDIV_PDIV_3 | ( 82 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 495, SYSCON_I2SDIV_PDIV_25 | ( 99 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 496, SYSCON_I2SDIV_PDIV_2 | (124 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 498, SYSCON_I2SDIV_PDIV_3 | ( 83 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 500, SYSCON_I2SDIV_PDIV_25 | (100 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 504, SYSCON_I2SDIV_PDIV_3 | ( 84 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 505, SYSCON_I2SDIV_PDIV_25 | (101 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 508, SYSCON_I2SDIV_PDIV_2 | (127 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 510, SYSCON_I2SDIV_PDIV_3 | ( 85 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 515, SYSCON_I2SDIV_PDIV_25 | (103 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 516, SYSCON_I2SDIV_PDIV_3 | ( 86 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 520, SYSCON_I2SDIV_PDIV_25 | (104 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 522, SYSCON_I2SDIV_PDIV_3 | ( 87 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 525, SYSCON_I2SDIV_PDIV_25 | (105 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 528, SYSCON_I2SDIV_PDIV_3 | ( 88 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 530, SYSCON_I2SDIV_PDIV_25 | (106 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 534, SYSCON_I2SDIV_PDIV_3 | ( 89 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 535, SYSCON_I2SDIV_PDIV_25 | (107 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 540, SYSCON_I2SDIV_PDIV_3 | ( 90 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 545, SYSCON_I2SDIV_PDIV_25 | (109 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 546, SYSCON_I2SDIV_PDIV_3 | ( 91 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 550, SYSCON_I2SDIV_PDIV_25 | (110 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 552, SYSCON_I2SDIV_PDIV_3 | ( 92 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 555, SYSCON_I2SDIV_PDIV_25 | (111 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 558, SYSCON_I2SDIV_PDIV_3 | ( 93 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 560, SYSCON_I2SDIV_PDIV_25 | (112 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 564, SYSCON_I2SDIV_PDIV_3 | ( 94 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 565, SYSCON_I2SDIV_PDIV_25 | (113 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 570, SYSCON_I2SDIV_PDIV_3 | ( 95 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 575, SYSCON_I2SDIV_PDIV_25 | (115 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 576, SYSCON_I2SDIV_PDIV_3 | ( 96 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 580, SYSCON_I2SDIV_PDIV_25 | (116 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 582, SYSCON_I2SDIV_PDIV_3 | ( 97 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 585, SYSCON_I2SDIV_PDIV_25 | (117 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 588, SYSCON_I2SDIV_PDIV_3 | ( 98 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 590, SYSCON_I2SDIV_PDIV_25 | (118 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 594, SYSCON_I2SDIV_PDIV_3 | ( 99 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 595, SYSCON_I2SDIV_PDIV_25 | (119 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 600, SYSCON_I2SDIV_PDIV_3 | (100 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 605, SYSCON_I2SDIV_PDIV_25 | (121 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 606, SYSCON_I2SDIV_PDIV_3 | (101 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 610, SYSCON_I2SDIV_PDIV_25 | (122 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 612, SYSCON_I2SDIV_PDIV_3 | (102 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 615, SYSCON_I2SDIV_PDIV_25 | (123 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 618, SYSCON_I2SDIV_PDIV_3 | (103 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 620, SYSCON_I2SDIV_PDIV_25 | (124 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 624, SYSCON_I2SDIV_PDIV_3 | (104 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 625, SYSCON_I2SDIV_PDIV_25 | (125 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 630, SYSCON_I2SDIV_PDIV_3 | (105 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 635, SYSCON_I2SDIV_PDIV_25 | (127 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 636, SYSCON_I2SDIV_PDIV_3 | (106 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 642, SYSCON_I2SDIV_PDIV_3 | (107 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 648, SYSCON_I2SDIV_PDIV_3 | (108 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 654, SYSCON_I2SDIV_PDIV_3 | (109 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 660, SYSCON_I2SDIV_PDIV_3 | (110 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 666, SYSCON_I2SDIV_PDIV_3 | (111 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 672, SYSCON_I2SDIV_PDIV_3 | (112 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 678, SYSCON_I2SDIV_PDIV_3 | (113 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 684, SYSCON_I2SDIV_PDIV_3 | (114 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 690, SYSCON_I2SDIV_PDIV_3 | (115 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 696, SYSCON_I2SDIV_PDIV_3 | (116 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 702, SYSCON_I2SDIV_PDIV_3 | (117 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 708, SYSCON_I2SDIV_PDIV_3 | (118 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 714, SYSCON_I2SDIV_PDIV_3 | (119 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 720, SYSCON_I2SDIV_PDIV_3 | (120 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 726, SYSCON_I2SDIV_PDIV_3 | (121 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 732, SYSCON_I2SDIV_PDIV_3 | (122 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 738, SYSCON_I2SDIV_PDIV_3 | (123 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 744, SYSCON_I2SDIV_PDIV_3 | (124 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 750, SYSCON_I2SDIV_PDIV_3 | (125 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 756, SYSCON_I2SDIV_PDIV_3 | (126 & SYSCON_I2SDIV_MDIV_MASK) },
+ { 762, SYSCON_I2SDIV_PDIV_3 | (127 & SYSCON_I2SDIV_MDIV_MASK) }
+};
- Follow-Ups:
- [linux-cirrus] Re: ep93xx I2S driver
- From: Lennert Buytenhek
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- » [linux-cirrus] Re: ep93xx I2S driver
- » [linux-cirrus] Re: ep93xx I2S driver
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- » [linux-cirrus] Re: ep93xx I2S driver
- » [linux-cirrus] Re: ep93xx I2S driver
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- From: Lennert Buytenhek