[linux-cirrus] Re: FastBus mode, core running on HCLK

Here is the code (which I cut-and-paste from the TS-BOOTROM source)

       // Go to async mode
       asm ("mrc p15, 0, r0, c1, c0, 0");
       asm ("orr r0, r0, #0xc0000000");
       asm ("mcr p15, 0, r0, c1, c0, 0");
You might double-check and make sure nobody is clobbering that coprocessor reg by doing a write when it should be doing a read-modify-write. 
//Jesse Off

Charles Moschel wrote:

Thanks Jesse.

I found that setting the nF bit (bit 30) in the control register, the
CPU is back running at 200 MHz.  Not a lot of testing so far, but
bogoMips are back up to: 99.73 BogoMIPS (lpj=498688), whetstones are
doubled (16 MIPS :), etc.

Can you check to be sure that nF set in the TS bootrom code?  If so,
I'll have to look into proc-arm920.S a little closer to see where it's
being unset. (This is my first attempt at arm assembly :) 
Do we want to honor (and rely on) the bootrom code, or should we set nF
explicitly in __arm920_setup? 

Regards, ........ Charlie


On Thu, 2007-02-01 at 08:40 -0700, Jesse Off wrote:

You should run the ARM core in async mode.  Fastbus is not what you want.
sync mode is the fastest (but only slightly), but requires a specific phase relationship between FCLK and HCLK. Unfortunately, theres not enough documentation in the Cirrus literature to know whether the PLL HCLK and FCLK have the correct phase relationship. 
FCLK needs to be high each time HCLK transitions.
The TS-7250 clock setup and ARM core clocking mode are set up in the TS-BOOTROM. 

//Jesse Off

Charles Moschel wrote:

Hi Folks --

I'm still trying to chase down a performance difference between 2.4 and
2.6 kernels on my TS-7250 [1].  Config options & compilers don't make a
difference, so I turned to the hardware & docs.  CLKSET1 and CLKSET2
appear to be set correctly, but the EP9301 users manual (4.1.5.2.1)
says:

" .. even though FCLK is the ARM processor clock, the ARM processor has
the option to run the CPU using HCLK. ...  Fast Bus mode bypasses FCLK,
and the ARM runs from HCLK. ... When the device starts up it defaults to
Fast Bus mode".

Well, this seems to match my symptoms: PLLs correct (FCLK=200 MHz,
HCLK=100 MHz) but performance exactly 1/2 of expected, as if the CPU
runs at 100 MHz.

The ARM920T Tech Ref Manual says that Fast Bus is controlled by bit 31
(iA - Async clock select) and bit 30 (nF - notFastBus) of CP15 Register
1 (ControlRegister).  I see (in arch/arm/kernel/mm/proc-arm920.S) that
we don't set either of these bits.  Should we?

Or are these bits the bootloader responsibility?  (If so, that could
explain why this is seen on TS boards but not others)  Or a difference
between ep9302 vs ep9315?  Docs are the same ...

Can I just set the right bits in crval, in __arm920_setup?  Sync or
Async?

Any suggestions?

Thanks ........ Charlie

[1]http://www.freelists.org/archives/linux-cirrus/01-2007/msg00065.html

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