Hi all, I've been suscribed to this forum for quitesome time now, and it is good to see that this is such a helpful community on the web. I am an MSEE student at UIUC learning to use the cadence allegro platform for SI-aware design, which is part of my master's thesis. (I use version 15.0). In the last few months I have been just following some online tutorials to get a sense of the software suite. As far as I know a typical workflow is something like: 1) schematic/simulation 2) pcb layout 3) signal integrity analysis on pcb 4) loop back as needed 1) I started with OrCad Capture CIS 10 for schematic layout. Simulation was easy. But as I tried to import a simple 3 bit ADC into Allegro to attempt a simple PCB layout, I had netlisting problems. 2) I gave up, so I tried just working on pcb layout itself, getting a little bit of experience in placement and routing AND gate 74_ packages. 3) Having a better sense of allegro for layout itself, i tried some SI analysis by following a simple driver to receiver interconnct tutorial at specctraquest.com (now gone i think) which used SigXplorer. Anyhow looking back, I'm not so sure what I've learned. I still cannot complete the transistion between 1) => 2). Nor do I have a good sense of what to do in completing 2) => 3). Any guidance/advice/tutorials would be much appreciated. I just want to complete a simple design loop. Regards, Samuel Kuo ----------------------------------------------------------- To subscribe/unsubscribe: Send a message to icu-pcb-forum-request@xxxxxxxxxxxxx with a subject of subscribe or unsubscribe To view the archives of this list please login at //www.freelists.org. Our list name is icu-pcb-forum or go to //www.freelists.org/archives/icu-pcb-forum/ Problems or Questions: Send an email to icu-pcb-forum-admins@xxxxxxxxxxxxx Want to post a job listing ? DON'T DO IT HERE! Better yet, join our jobs listing forum. SUBSCRIBE: icu-jobs-forum-subscribe@xxxxxxxxxx POST: icu-jobs-forum@xxxxxxxxxx -----------------------------------------------------------