[PCB_FORUM] tangential vias DRCs not behaving as expected

Hi all,

I tried logging onto SourceLink, but it appears they may be down. If
anyone can shed some light on this please do.

The following is an oversimplified example of a problem we're having. In
some areas we need to allow vias to be tangent to, or slightly
overlapping pads. In other areas we do not want that. The blue line is a
constraint area with a net_spacing_property of tangent_ok. The spacing
assignment table assigns a rule, also called tangent_ok, which is a copy
of the DEFAULT rule except that same_net_drc is set to off. As you see,
we still get drc's. If, however, we change the DEFAULT rule to set
same_net_drc to off, then the drc's go away. But, of course, they go
away for both cases, not just the ones in the constraint area. I've
attached this little board file to the mail in case anyone has a few
minutes to play with this and see if we're doing something wrong.

Thanks for any help,

Jean

 

 

 

Jean Bratton

Sr. Printed Circuit Designer

Freedom CAD Services, Inc.

603-864-1300 x1349

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