[PCB_FORUM] Re: same net rules

  • From: "Chew Wang" <chew.wang@xxxxxxxxx>
  • To: icu-pcb-forum@xxxxxxxxxxxxx
  • Date: Thu, 25 Jan 2007 13:27:26 +0530

Hi All,

TQ first of all.I have learnt lot of new options thru this thread.

Is there any option in Allegro 15.5 to check trace to soldermask clearance.

I think this option is there in 15.7

Regards
Chew.


On 1/22/07, westfeldt <westfeldt_nbcd@xxxxxxxxx> wrote:

Hi Mike

The "sm to sm" drc establishes minimum soldermask to soldermask boundary
spacing, and can be used in lieu of a same net via to smd rule, which
effectively ensures(depending on padstack values) a minimum soldermask web
between the untented via hole and the smd pad.  For different nets, the
via
to smd works fine, but if you want to apply this rule to same
nets(obviously
even more important because of the direct connection) you have to select
the
global same net box for all rules.

For pins and vias, this "sm to sm" rule specifically preserves your
minimum
design soldermask web.  In addition to the via-to-smd aspects, it looks
like
this rule will change my view of fine pitch (.5 mm) chips, as I will not
be
able to have padstacks with 2.5-3mil annular soldermask rings.  Although
the
soldermask spacing may not be as critical for smd to smd as it is for via
to
smd, this Allegro rule will treat them the same. I'm glad that most of my
annular rings are 2 mils anyway, but I always have to fight with fab shops
about it.

And Jean-Charles is right, this is a weak point in the rules.  Even PADS
has
a complete set of selectable same net rules.

Patrick

-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of
gnieski_mike@xxxxxxx
Sent: Monday, January 22, 2007 5:01 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: same net rules

       Just reading this email and also have never seen this rule before.
       What is the function of the soldermask alignment drc?

       Mike

-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of westfeldt
Sent: Saturday, January 20, 2007 7:18 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: same net rules

Thank you Robert.  I can't believe I have never seen that one in there.
Using "sm to sm" works for via to smd.  Also a pleasant surprise, this
does
not give me drc's where I allow a soldermask shape to cover over pads that
already have soldermasks.  I'm guessing this rule will show up with
occasional bogus drc's, but nowhere near as bad as if I pushed the same
net
button.

Patrick

-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Robert Szumowicz
Sent: Tuesday, January 09, 2007 1:10 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: same net rules

Patrick,
I think it is available even in a lower tool than Performance:
setup-> constrains->design constrains->soldermask to soldermask

Dave,
they do if same net DRC is switched on, but:
- I cannot assign different values for 'same net' and 'different net'
- I see occasionally unwanted and annoying DRCs 'Line to Line Spacing'
when clines overlaps (intentionally)

Robert


westfeldt wrote:
> Soldermask to soldermask might work, but I don't know how to set it,
> is that available in Performance option?
>
> -----Original Message-----
> From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
> [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Robert
> Szumowicz
> Sent: Friday, January 19, 2007 8:24 AM
> To: icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] Re: same net rules
>
> Hi all,
>
> I think I do understand the question since I also miss such feature.
>
> Problem stated:
>  - to not to have Via too close to SMD pin
>
> Partial Solution:
>  - enable same net DRC (problem is that it checks all other rules and
> often creates many unwanted DRCs)
>
> Other possibility
>  - set a rule for "Solder mask to Solder mask" spacing assuming that
> Vias are not covered (problem is that this is one global rule for a
> whole design)
>
> regards,
> Robert
>
>
> Macindoe, Gary wrote:
>
>> Hey Pat,
>>
>> Not exactly sure what you are asking here.  Need a little
clarification!
>>
>> Gary E. MacIndoe
>> Advanced Micro Devices
>> PCB Design Engineer
>> Longmont, Colorado
>>
>> -----Original Message-----
>> From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
>> [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of westfeldt
>> Sent: Friday, January 19, 2007 6:43 AM
>> To: icu-pcb-forum@xxxxxxxxxxxxx
>> Subject: [PCB_FORUM] same net rules
>>
>> Is there no way in Allegro to have the same net rules apply only to
>> certain rules?  The one I always need is via to smd pin, but I would
>> not want all the rest of the rules to have same net application.
>>
>> Patrick Westfeldt, Jr.
>> North Boulder Circuit Design
>> westfeldt_nbcd@xxxxxxxxx
>> 720-406-0887
>> c 720-272-5822
>>
>>
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