[PCB_FORUM] question about Concept symbols

Hi All,

 

I have been working on concept symbols in version 15.5 .One requirement is
that "All parts must be able to be verilog simulated".

Is there any special thing that I need to do in order to have symbols being
able to be verilog simulated.

 

Zafar Bhatti

Design Engineer

Whizz Systems Inc.

Office:(408) 980-0400 Ext. 112

zbhatti@xxxxxxxxxxxxxxxx

 

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