[PCB_FORUM] Re: package order

Carlos, 
no problem,
Let me know if I can help... I have worked through many of the issues!

The document Mike sent out (From Harris) was pretty good,
And some of the issues they talk about have been fixed.

After working with hierarchy for some time, I try never to use
Global powers down through the hierarchy... I put a power port on the
Block and connect it up at the high level. This lets you use the same block
Across multiple designs without the headache of trying to fix up power nets 
The Harris paper talks about using parameters to name power signals. That?s
not a bad idea, but the ports are more straight forward (although they do
take up room on a block with a lot of IO)

Bill

-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of cbelio
Sent: Friday, March 30, 2007 6:44 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: package order

Bill, thank you very much. It sounds extremely useful.

I will try the subdesigns out and will come back to you if I don't know how
to go on.

Regards,
Carlos Belío
Telnet RI



>>-----Mensaje original-----
>>De: icu-pcb-forum-bounce@xxxxxxxxxxxxx [mailto:icu-pcb-forum-
>>bounce@xxxxxxxxxxxxx] En nombre de Bill O'Leary
>>Enviado el: sábado, 24 de marzo de 2007 16:43
>>Para: icu-pcb-forum@xxxxxxxxxxxxx
>>Asunto: [PCB_FORUM] Re: package order
>>
>>I didn't see you get an answer to this
>>
>>The packager initially assigns refdes using the xy coordinates of the part
>>on the page. (instances are assigned in the order you placed them)
>>
>>The module order controls how the schematic prints, I'm pretty sure it has
>>nothing to do with packaging.
>>
>>Carlos,
>>Did you receive this answer?
>>
>>I think the packager goes through the top level schematic, and then drops
>>into each hierarchical block as it finds it in the same XY order.
>>
>>If you want to control refdes of hierarchy, you need to use sub-designs,
>>and
>>The subdesignsuffix property.
>>
>>Using subdesigns, each subblock is packaged on its own, so it starts at
>>R1,
>>C1, U1.... and then when the design is put together by the packager, it
>>appends an _XX (where XX is the subdesign suffix property you added to the
>>block symbol (and the underscore is controlled by a subdesign separator
>>property)
>>
>>You can go as many levels deep as you want using this, so you can end up
>>With a refdes like R_CA1 U_CA1, R_CB1, U_CB1, R_CA2, U_CA2....
>>
>>What you have to realize if you use this is that you need to package each
>>Sub-block separately, and each sublevel has to know what blocks it will be
>>using as a subdesign (there are FORCE_SUBDESIGN and GEN_SUBDESIGN
>>properties
>>which need to be used while packaging (these are in the advanced options
>>tab
>>when you package))
>>
>>I found these very useful (and used it across a series of complex
>>designs),
>>but once I had more than 2 levels deep in a schematic, I had to write my
>>own
>>tool around the packager to keep my sanity.
>>
>>The nice thing about the subdesigns is you can use a block in multiple
>>designs and they will all have the same refdes!
>>
>>
>>Hope this helps,
>>
>>Bill O'Leary
>>
>>CadEnhance LLC.
>>

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