[PCB_FORUM] Re: missing files in 'packaged' directory

Thank you for your help. That worked just fine.



Martin G. Nolting
PCB Layout Engineer

LSI Logic Corporation, ESG
5400 Airport Blvd Suite 100
Boulder, CO 80301

303.381.4284 (phone)
martin.nolting@xxxxxxx<mailto:martin.nolting@xxxxxxx>

Enable. Enhance. Empower.

________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx 
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Mike Golding
Sent: Tuesday, November 25, 2008 11:19 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: missing files in 'packaged' directory

REVERTING A CADENCE CM ENABLED PROJECT BACK TO A NON CM ENABLED PROJECT

SITUATION:
The layout design is done in Allegro, with Cadence schematic on front end.
The PCB Designer is responsible for setting up design constraints in Allegro 
environment.

PROBLEM:
The person who controls the schematic will start the Constraint Manager Tool 
and ignore warning. This will cause a constraints view to be created and the 
project is now "CM Enabled". The constraint information from the schematic will 
now be included in the netlist files. When these files are read into the 
Allegro session, constraints that were setup through the Allegro environment 
are deleted or modified.

HOW TO DETECT PROBLEM:
The designer should verify that typically only the following netlist files are 
supplied, or present in the directory that is being referenced during the Logic 
>Import process:
pstchip.dat
pstxprt.dat
pstxnet.dat

If the designer attempts to read in these three files and receives the below 
error, the designer should ask the schematic user to run the Revert Process 
described in this document. Do not request the additional files that are listed 
in the error message.

"#1 ERROR(300) Net Rev fatal error detected. Design flow is Constraint Manager 
enabled, require pstcmdb.dat and pstcmbc.dat files."

If the designer sees that the board's Branding is listed as "...Constraint 
Manager Enabled Flow" in the Import Logic dialogue box (as shown below), this 
means the design has already read in constraints from the schematic. The Revert 
Process should be run, and all rules should be re-verified.
[cid:image001.jpg@01C94EF3.25BD1D20]<http://tg.plexus.com/wiki/index.php/Image:Cm_enable_flow.jpg>
REVERT PROCESS:

In this example,
/widget_project = your project directory
/widget_design = your design directory

1.) Make a back-up copy of your project.

2.) Remove the /constraints subdirectory located at:
.../widget_project/worklib/widget_design/constraints

3.) Remove the "cm" state files
Go to directory .../widget_project/worklib/widget_design/packaged
Remove the files: pstcmdb.dat, pstcmback.dat and pstcmbc.dat
If the files cmdbview.dat and cmbcview.dat exist, remove them also.

Go to directory .../widget_project/worklib/widget_design/packaged
Remove the file: pstcmdb2.dat

4.) If you have already imported the constraint enabled netlist to the Allegro 
board then the board file has been branded "CM-Enabled". You will need to 
unbrand the board file.
The "Branding" status can be found on the Import Logic dialogue box, as shown 
in the earlier screenshot.

In the Allegro command console type: skill <enter>
From the Skill prompt type: axlDBControl('cmgrEnabledFlow nil) <enter>
You should see a "t" returned which tells you that the command was successful.
Type: exit <enter>
Save the board.

5.) In these scenarios you will need to remove the opf (occurrence property 
file):

 *   If a ConceptHDL user has called Constraint Manager and added actual 
constraints to the
design these have been written to the constraint view of the design and updated 
to the opf .

 *   If the constraints have been back annotated from Allegro (using File -> 
Export -> Logic) with "Export usingConstraint Manager Enabled Flow " checked 
and subsequently updated to the schematic (using Tools -> Constraints-> Update 
Schematic) the opf has been updated also.

To Remove The opf:
Go to .../widget_project/worklib/widget_design
Removed the /opf subdirectory.


Thanks,
Mike Golding                   \  
mike.golding@xxxxxxxxxx<mailto:mike.golding@xxxxxxxxxx>
Senior PCB Designer        \  +1-920-969-6114 Phone
Plexus Technology Group  \ +1-920-428-3280 Cell
55 Jewelers Park Drive       \  +1-920-751-5366 Fax
Neenah, WI  54957             \  www.plexus.com<http://www.plexus.com>
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx 
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Nolting, Martin
Sent: Tuesday, November 25, 2008 12:12 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] missing files in 'packaged' directory

Anyone know how to correct this error?


[cid:image002.jpg@01C94EF3.25BD1D20]


I don't see where to set the output from Design HDL to export these two files.
Not sure how the flow got set to be "Constraint Manager enabled" to begin with, 
can that be changed? We haven't used these two files previously.

If I can't set the flow to not be constraint manager driven, then how do I get 
those two files generated?

Any help would be appreciated.

Have a great day!


Martin G. Nolting
PCB Layout Engineer

LSI Logic Corporation, ESG
5400 Airport Blvd Suite 100
Boulder, CO 80301

303.381.4284 (phone)
martin.nolting@xxxxxxx<mailto:martin.nolting@xxxxxxx>

Enable. Enhance. Empower.

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