[PCB_FORUM] Re: linewidth change
- From: Larry Briski <lgb@xxxxxxx>
- To: icu-pcb-forum@xxxxxxxxxxxxx
- Date: Thu, 09 Sep 2004 12:59:50 -0500
Patricki
I'm still in 14.2. The line width action you describe occurs in 14.2
also. I've seen it in previous versions of Allegro too.
Larry
westfeldt wrote:
Thank you David, but that was not it. It was unset, but setting it had
no effect.
Further details. This effect does not occur if I start route with some
specified width and change layers. It only occurs when I start routing
on an existing trace so that this existing width is my routing width.
When I drop the via, it reverts to the default drc trace width.
------------------------------------------------------------------------
From: David Greig [mailto:David@xxxxxxxxxxxxxx]
Sent: Thursday, September 09, 2004 10:47 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: linewidth change
Is the environment variable acon_no_impedance width unset? This would
let the tool adjust line width to compensaye for impedances on each layer.
I set it because I don't agree with the Allegro methodology for
calculating impedance. Correct impedance calculations are easy enough to
do (or you can resort to Method Of Moments 2D tools) Either will give
more satisfactory results.
Another reason for not letting the tool decide is if you want to
identify controlled impedance routes by layer to the fab shop. Just make
sure that your plane fill aperture is different from the controlled line
width or the fab shop will have a harder time of it!
Best Regards
David Greig
_________________________________________
Director
GigaDyne Ltd
Buchan House
Carnegie Campus
Dunfermline KY11 8PL
United Kingdom
Tel. +44 (0) 1383 62 49 75
_________________________________________
------------------------------------------------------------------------
From: westfeldt [mailto:westfeldt_nbcd@xxxxxxxxx]
Sent: 09 September 2004 16:27
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] linewidth change
Still getting used to v15.1. Sometimes tracewidth goes from my current
width to minimum drc value when I drop a via; didn't do that in my
v14.2. How do I fix this?
Patrick Westfeldt, Jr.
North Boulder Circuit Design
westfeldt_nbcd@xxxxxxxxx
720-406-0887
c 720-272-5822
--
Virus scanned by Lumison.
--
Lawrence Briski
SGI
Chippewa Falls, WI 54729
Phone: 715.726.7440
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