[PCB_FORUM] Re: icu-pcb-forum Digest V2 #5
- From: "Tran, Marcel" <marcel.tran@xxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Thu, 20 Jan 2005 10:02:05 -0800
To whom it may concern,
I would like to receive the full text Email every day as before. Thank you,
Regards,
Marcel Tran
Sr. PCB-CAD Engineer
Off. (253) 371-4779
Fax (253) 371-5010
Email : marcel.tran@xxxxxxxxx
-----Original Message-----
From: FreeLists Mailing List Manager [mailto:ecartis@xxxxxxxxxxxxx]
Sent: Thursday, January 20, 2005 9:29 AM
To: icu-pcb-forum digest users
Subject: icu-pcb-forum Digest V2 #5
icu-pcb-forum Digest Mon, 17 Jan 2005 Volume: 02 Issue: 005
In This Issue:
[PCB_FORUM] 15.2 Manufacture Film Parameter Camera
[PCB_FORUM] Re: 15.2 Manufacture Film Parameter Camera
[PCB_FORUM] Re: 15.2 Manufacture Film Parameter Camera
[PCB_FORUM] Re: 15.2 Manufacture Film Parameter Camera
[PCB_FORUM] Re: 15.2 Manufacture Film Parameter Camera
[PCB_FORUM] LOCATION feedback
[PCB_FORUM] Re: LOCATION feedback
[PCB_FORUM] Re: LOCATION feedback
[PCB_FORUM] Antwort: LOCATION feedback
[PCB_FORUM] Re: LOCATION feedback
[PCB_FORUM] Unschedule a Group of User Scheduled Nets
[PCB_FORUM] Re: Unschedule a Group of User Scheduled Nets
[PCB_FORUM] Testprep Problem
[PCB_FORUM] Re: Unschedule a Group of User Scheduled Nets
[PCB_FORUM] Re: Unschedule a Group of User Scheduled Nets
[PCB_FORUM] Diff pair separation.
[PCB_FORUM] Re: Diff pair separation.
[PCB_FORUM] Re: Diff pair separation.
[PCB_FORUM] multiple route
[PCB_FORUM] Re: Testprep Problem
[PCB_FORUM] Re: Testprep Problem
[PCB_FORUM] Re: Testprep Problem
[PCB_FORUM] Re: Testprep Problem
[PCB_FORUM] allegro to power pcb
[PCB_FORUM] Re: allegro to power pcb
[PCB_FORUM] Re: allegro to power pcb
[PCB_FORUM] Re: allegro to power pcb
[PCB_FORUM] Re: allegro to power pcb
[PCB_FORUM] Re: allegro to power pcb
[PCB_FORUM] Re: allegro to power pcb
[PCB_FORUM] Re: allegro to power pcb
[PCB_FORUM] Re: allegro to power pcb
[PCB_FORUM] Re: allegro to power pcb
[PCB_FORUM] Re: allegro to power pcb
[PCB_FORUM] Re: allegro to power pcb
[PCB_FORUM] Re: allegro to power pcb
[PCB_FORUM] Re: allegro to power pcb
[PCB_FORUM] Pads Netlist - 2- Allegro netlist
[PCB_FORUM] Re: multiple route
[PCB_FORUM] Re: multiple route
[PCB_FORUM] Re: multiple route
[PCB_FORUM] Re: multiple route
[PCB_FORUM] Re: multiple route
[PCB_FORUM] Re: multiple route
----------------------------------------------------------------------
Subject: [PCB_FORUM] 15.2 Manufacture Film Parameter Camera
Date: Mon, 17 Jan 2005 17:26:09 -0500
From: "Moore, Blake" <Blake.Moore@xxxxxxxxxx>
> I just started 15.2 today.
> When I add the tool manufacture toolbar (Odb_out) (Ncdrill Legend)
> (Ncdrill Parameter) (Film Parameter "Camera")
>
> Everything works except the "Film Parameter" The Camera Icon is greyed
> out?
> It all still works ok in 15.1
> But in 15.2 I can't get the camera icon on the tool bar to work.
>
> Anybody else have that problem, and or could share what they did to
> fix it.
>
> Thank's
> Blake
> PCB Design
> ADI Greensboro, NC
------------------------------
From: george.h.patrick@xxxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: 15.2 Manufacture Film Parameter Camera
Date: Mon, 17 Jan 2005 14:31:30 -0800
This has been fixed.
You need to get the latest patch level from Cadence and install it.
You can still get to the artwork window from the menu:
Manufacture > Artwork
--
George Patrick
Tektronix, Inc.
Central Engineering, PCB Design Group
P.O. Box 500, M/S 39-512
Beaverton, OR 97077-0001
Phone: 503-627-5272 Fax: 503-627-5587
http://www.tektronix.com http://www.pcb-designer.com
It's my opinion, not Tektronix'
-----Original Message-----
From: Moore, Blake [mailto:Blake.Moore@xxxxxxxxxx]
Sent: Monday, January 17, 2005 14:26
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] 15.2 Manufacture Film Parameter Camera
> I just started 15.2 today.
> When I add the tool manufacture toolbar (Odb_out) (Ncdrill Legend)
> (Ncdrill Parameter) (Film Parameter "Camera")
>
> Everything works except the "Film Parameter" The Camera Icon is greyed
> out?
> It all still works ok in 15.1
> But in 15.2 I can't get the camera icon on the tool bar to work.
>
> Anybody else have that problem, and or could share what they did to
> fix it.
>
> Thank's
> Blake
> PCB Design
> ADI Greensboro, NC
-----------------------------------------------------------
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------------------------------
Subject: [PCB_FORUM] Re: 15.2 Manufacture Film Parameter Camera
Date: Mon, 17 Jan 2005 17:43:46 -0500
From: "Moore, Blake" <Blake.Moore@xxxxxxxxxx>
A Ok, thank you so much, I just did the menu, it's there just like you
said, that will get me through the night, and I can request the patch
tomorrow, they have the software so I can't add etc...I have to request
from our support group. But at least now I know what to ask for etc...
You really helped me out, again thx's really appreciate it.
-----Original Message-----
From: george.h.patrick@xxxxxxxxxxxxxx
[mailto:george.h.patrick@xxxxxxxxxxxxxx]
Sent: Monday, January 17, 2005 5:32 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: 15.2 Manufacture Film Parameter Camera
This has been fixed.
You need to get the latest patch level from Cadence and install it.
You can still get to the artwork window from the menu:
Manufacture > Artwork
--
George Patrick
Tektronix, Inc.
Central Engineering, PCB Design Group
P.O. Box 500, M/S 39-512
Beaverton, OR 97077-0001
Phone: 503-627-5272 Fax: 503-627-5587
http://www.tektronix.com http://www.pcb-designer.com
It's my opinion, not Tektronix'
-----Original Message-----
From: Moore, Blake [mailto:Blake.Moore@xxxxxxxxxx]
Sent: Monday, January 17, 2005 14:26
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] 15.2 Manufacture Film Parameter Camera
> I just started 15.2 today.
> When I add the tool manufacture toolbar (Odb_out) (Ncdrill Legend)
> (Ncdrill Parameter) (Film Parameter "Camera")
>
> Everything works except the "Film Parameter" The Camera Icon is greyed
> out?
> It all still works ok in 15.1
> But in 15.2 I can't get the camera icon on the tool bar to work.
>
> Anybody else have that problem, and or could share what they did to
> fix it.
>
> Thank's
> Blake
> PCB Design
> ADI Greensboro, NC
-----------------------------------------------------------
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-----------------------------------------------------------
------------------------------
Date: Mon, 17 Jan 2005 17:45:58 -0500
From: Kevin McCowan <kmccowan@xxxxxxxxxxxxxx>
Subject: [PCB_FORUM] Re: 15.2 Manufacture Film Parameter Camera
Well, that's why we are here.
Oh, and we make boards, too!
(I know, I didn't help on this one but I couldn't
help commenting.)
Kevin McCowan
Moore, Blake wrote:
> A Ok, thank you so much, I just did the menu, it's there just like you
> said, that will get me through the night, and I can request the patch
> tomorrow, they have the software so I can't add etc...I have to request
> from our support group. But at least now I know what to ask for etc...
> You really helped me out, again thx's really appreciate it.
>
>
> -----Original Message-----
> From: george.h.patrick@xxxxxxxxxxxxxx
> [mailto:george.h.patrick@xxxxxxxxxxxxxx]
> Sent: Monday, January 17, 2005 5:32 PM
> To: icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] Re: 15.2 Manufacture Film Parameter Camera
>
>
> This has been fixed.
>
> You need to get the latest patch level from Cadence and install it.
>
> You can still get to the artwork window from the menu:
> Manufacture > Artwork
>
> --
> George Patrick
> Tektronix, Inc.
> Central Engineering, PCB Design Group
> P.O. Box 500, M/S 39-512
> Beaverton, OR 97077-0001
> Phone: 503-627-5272 Fax: 503-627-5587
> http://www.tektronix.com http://www.pcb-designer.com
>
> It's my opinion, not Tektronix'
>
>
>
> -----Original Message-----
> From: Moore, Blake [mailto:Blake.Moore@xxxxxxxxxx]
> Sent: Monday, January 17, 2005 14:26
> To: icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] 15.2 Manufacture Film Parameter Camera
>
>
>
>>I just started 15.2 today.
>>When I add the tool manufacture toolbar (Odb_out) (Ncdrill Legend)
>>(Ncdrill Parameter) (Film Parameter "Camera")
>>
>>Everything works except the "Film Parameter" The Camera Icon is greyed
>>out?
>>It all still works ok in 15.1
>>But in 15.2 I can't get the camera icon on the tool bar to work.
>>
>>Anybody else have that problem, and or could share what they did to
>>fix it.
>>
>>Thank's
>>Blake
>>PCB Design
>>ADI Greensboro, NC
>
> -----------------------------------------------------------
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> -----------------------------------------------------------
------------------------------
From: george.h.patrick@xxxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: 15.2 Manufacture Film Parameter Camera
Date: Mon, 17 Jan 2005 14:47:37 -0800
Glad to help :)
--
George Patrick
Tektronix, Inc.
Central Engineering, PCB Design Group
P.O. Box 500, M/S 39-512
Beaverton, OR 97077-0001
Phone: 503-627-5272 Fax: 503-627-5587
http://www.tektronix.com http://www.pcb-designer.com
It's my opinion, not Tektronix'
-----Original Message-----
From: Moore, Blake [mailto:Blake.Moore@xxxxxxxxxx]
Sent: Monday, January 17, 2005 14:44
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: 15.2 Manufacture Film Parameter Camera
A Ok, thank you so much, I just did the menu, it's there just like you
said, that will get me through the night, and I can request the patch
tomorrow, they have the software so I can't add etc...I have to request
from our support group. But at least now I know what to ask for etc...
You really helped me out, again thx's really appreciate it.
-----Original Message-----
From: george.h.patrick@xxxxxxxxxxxxxx
[mailto:george.h.patrick@xxxxxxxxxxxxxx]
Sent: Monday, January 17, 2005 5:32 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: 15.2 Manufacture Film Parameter Camera
This has been fixed.
You need to get the latest patch level from Cadence and install it.
You can still get to the artwork window from the menu:
Manufacture > Artwork
--
George Patrick
Tektronix, Inc.
Central Engineering, PCB Design Group
P.O. Box 500, M/S 39-512
Beaverton, OR 97077-0001
Phone: 503-627-5272 Fax: 503-627-5587
http://www.tektronix.com http://www.pcb-designer.com
It's my opinion, not Tektronix'
-----Original Message-----
From: Moore, Blake [mailto:Blake.Moore@xxxxxxxxxx]
Sent: Monday, January 17, 2005 14:26
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] 15.2 Manufacture Film Parameter Camera
> I just started 15.2 today.
> When I add the tool manufacture toolbar (Odb_out) (Ncdrill Legend)
> (Ncdrill Parameter) (Film Parameter "Camera")
>
> Everything works except the "Film Parameter" The Camera Icon is greyed
> out?
> It all still works ok in 15.1
> But in 15.2 I can't get the camera icon on the tool bar to work.
>
> Anybody else have that problem, and or could share what they did to
> fix it.
>
> Thank's
> Blake
> PCB Design
> ADI Greensboro, NC
-----------------------------------------------------------
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-----------------------------------------------------------
------------------------------
Keywords: CERN SpamKiller Note: -50 Charset: west-latin
From: "William Billereau" <william.billereau@xxxxxxx>
Subject: [PCB_FORUM] LOCATION feedback
Date: Tue, 18 Jan 2005 11:20:28 +0100
Hello All.
The packager assigns, the first time it runs, $LOCATION on Concept parts.
After component placement and swaps, we backannote them on the BRD and feedback
changes to Concept.
Then some $LOCATION are changed to LOCATION (not all, but especially component
were swap pins or functions was made)
The same thing occurs with $PN properties that become PN
If you copy in the design a component with a LOCATION, it copies the whole
property (name and value) to the copy and the next packaging will fail with
such errors because of two instances of LOCATION:
#1 ERROR(1109): Cannot package instance into package C59.
Schematic instance: @TTCCI_LIB.TTCCI_TOP(SCH_1):PAGE1_I5@xxxxxxxxxxxxx~
CI_VME(SCH_1):PAGE1_I469@xxxxxxxxxxxxxxxxxxxxxx(CHIPS) (MODULE: TTCCI_VME; PAR~
T: CAPCERSMDCL2)
Section 1 is assigned @TTCCI_LIB.TTCCI_TOP(SCH_1):PAGE1_I5@xxxxxxxxxxx~
TCCI_VME(SCH_1):PAGE1_I143@xxxxxxxxxxxxxxxxxxxxxx(CHIPS) (MODULE: TTCCI_VME; P~
ART: CAPCERSMDCL2)
#2 ERROR(101): Primitive @TTCCI_LIB.TTCCI_TOP(SCH_1):PAGE1_I5@xxxxxxxxxxxxxx~
I_VME(SCH_1):PAGE1_I469@xxxxxxxxxxxxxxxxxxxxxx(CHIPS) is not packaged.
#3 ERROR(100): State file not written for design TTCCI_TOP.
And swaps (in the case of PN) are no more allowed (NO_SWAP_GATE properties are
attached to functions.
Does anybody know how to avoid this?
Thanks in advance.
William.
------------------------------
Date: Tue, 18 Jan 2005 08:38:05 -0500
From: rjbzxr@xxxxxxxxxxxx
Subject: [PCB_FORUM] Re: LOCATION feedback
Hi William,
Not sure how this happened.. maybe someone else can comment.
But you can do this to get the $location back..
a) Group->Create By expression. Enter LOCATION. Hit OK.
b) Group->Text Change
c) Right click in schematic editor and select Editor menu from RMB.
d) Do a Replace ALL by changing LOCATION to $LOCATION. Do a repackage and
everything should be fine.
"William Billereau" <william.billereau@xxxxxxx> wrote:
>Hello All.
>
>The packager assigns, the first time it runs, $LOCATION on Concept parts.
>
>After component placement and swaps, we backannote them on the BRD and
>feedback changes to Concept.
>Then some $LOCATION are changed to LOCATION (not all, but especially component
>were swap pins or functions was made)
>The same thing occurs with $PN properties that become PN
>
>If you copy in the design a component with a LOCATION, it copies the whole
>property (name and value) to the copy and the next packaging will fail with
>such errors because of two instances of LOCATION:
>#1 ERROR(1109): Cannot package instance into package C59.
> Schematic instance: @TTCCI_LIB.TTCCI_TOP(SCH_1):PAGE1_I5@xxxxxxxxxxxxx~
>CI_VME(SCH_1):PAGE1_I469@xxxxxxxxxxxxxxxxxxxxxx(CHIPS) (MODULE: TTCCI_VME; PAR~
>T: CAPCERSMDCL2)
> Section 1 is assigned @TTCCI_LIB.TTCCI_TOP(SCH_1):PAGE1_I5@xxxxxxxxxxx~
>TCCI_VME(SCH_1):PAGE1_I143@xxxxxxxxxxxxxxxxxxxxxx(CHIPS) (MODULE: TTCCI_VME; P~
>ART: CAPCERSMDCL2)
> #2 ERROR(101): Primitive @TTCCI_LIB.TTCCI_TOP(SCH_1):PAGE1_I5@xxxxxxxxxxxxxx~
>I_VME(SCH_1):PAGE1_I469@xxxxxxxxxxxxxxxxxxxxxx(CHIPS) is not packaged.
> #3 ERROR(100): State file not written for design TTCCI_TOP.
>
>And swaps (in the case of PN) are no more allowed (NO_SWAP_GATE properties are
>attached to functions.
>
>Does anybody know how to avoid this?
>
>Thanks in advance.
>
> William.
>
>
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------------------------------
From: "Gary MacIndoe" <gary.macindoe@xxxxxxx>
Subject: [PCB_FORUM] Re: LOCATION feedback
Date: Tue, 18 Jan 2005 08:51:49 -0700
Keywords: CERN SpamKiller Note: -50 Charset: west-latin
William,
This has been a real PITA for me for a long time now. After I do rpak
swaps, the engineer (using Concept HDL) does an import physical, then an
export physical to complete a full loop to make sure we are in sync. If
things change and I want to redo the rpak swaps, this bothersome
NO_SWAP_GATE property (sometimes also NO_SWAP_GATE_EXT is there) is on some
of the rpak sections and I have to remove it before I can swap function
again.
We thought we had it figured out once but it turned out not to work (it
looks like it should have worked!), in Program Manager:
- load in your *.cpm file
- click on Setup
- in the Tools tab, click on Setup... next to Packager-XL
- in the Properties tab, click on Property Flow Setup...
- in the Name column, find NO_SWAP_GATE (and NO_SWAP_GATE_EXT)
- click the box to remove the check in the Defined In Concept column for
the above properties
- OK out of the Program Manager Setup windows
This should prevent Concept from reapplying the above properties, but it
didn't work for us. We haven't tried it for a while, maybe it really works
now!
Good luck!
Gary E. MacIndoe
PCB Design Engineer
Advanced Micro Devices, Inc.
Longmont, Colorado
-----Original Message-----
From: William Billereau [mailto:william.billereau@xxxxxxx]
Sent: Tuesday, January 18, 2005 3:20 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] LOCATION feedback
Hello All.
The packager assigns, the first time it runs, $LOCATION on Concept parts.
After component placement and swaps, we backannote them on the BRD and
feedback changes to Concept.
Then some $LOCATION are changed to LOCATION (not all, but especially
component were swap pins or functions was made)
The same thing occurs with $PN properties that become PN
If you copy in the design a component with a LOCATION, it copies the whole
property (name and value) to the copy and the next packaging will fail with
such errors because of two instances of LOCATION:
#1 ERROR(1109): Cannot package instance into package C59.
Schematic instance:
@TTCCI_LIB.TTCCI_TOP(SCH_1):PAGE1_I5@xxxxxxxxxxxxx~
CI_VME(SCH_1):PAGE1_I469@xxxxxxxxxxxxxxxxxxxxxx(CHIPS) (MODULE: TTCCI_VME;
PAR~
T: CAPCERSMDCL2)
Section 1 is assigned
@TTCCI_LIB.TTCCI_TOP(SCH_1):PAGE1_I5@xxxxxxxxxxx~
TCCI_VME(SCH_1):PAGE1_I143@xxxxxxxxxxxxxxxxxxxxxx(CHIPS) (MODULE:
TTCCI_VME; P~
ART: CAPCERSMDCL2)
#2 ERROR(101): Primitive
@TTCCI_LIB.TTCCI_TOP(SCH_1):PAGE1_I5@xxxxxxxxxxxxxx~
I_VME(SCH_1):PAGE1_I469@xxxxxxxxxxxxxxxxxxxxxx(CHIPS) is not packaged.
#3 ERROR(100): State file not written for design TTCCI_TOP.
And swaps (in the case of PN) are no more allowed (NO_SWAP_GATE properties
are attached to functions.
Does anybody know how to avoid this?
Thanks in advance.
William.
------------------------------
Subject: [PCB_FORUM] Antwort: LOCATION feedback
From: Bruno.Renner@xxxxxxxxxxxxxxxx
Date: Tue, 18 Jan 2005 16:56:22 +0100
William,
if this is a hierarchical design you should not backannotate to the
hierarchical Block (TTCCI_VME), use NO_BACKANNOTATE property at block.
regards
Bruno
Hello All.
The packager assigns, the first time it runs, $LOCATION on Concept parts.
After component placement and swaps, we backannote them on the BRD and
feedback changes to Concept.
Then some $LOCATION are changed to LOCATION (not all, but especially
component were swap pins or functions was made)
The same thing occurs with $PN properties that become PN
If you copy in the design a component with a LOCATION, it copies the whole
property (name and value) to the copy and the next packaging will fail with
such errors because of two instances of LOCATION:
#1 ERROR(1109): Cannot package instance into package C59.
Schematic instance:
@TTCCI_LIB.TTCCI_TOP(SCH_1):PAGE1_I5@xxxxxxxxxxxxx~
CI_VME(SCH_1):PAGE1_I469@xxxxxxxxxxxxxxxxxxxxxx(CHIPS) (MODULE: TTCCI_VME;
PAR~
T: CAPCERSMDCL2)
Section 1 is assigned
@TTCCI_LIB.TTCCI_TOP(SCH_1):PAGE1_I5@xxxxxxxxxxx~
TCCI_VME(SCH_1):PAGE1_I143@xxxxxxxxxxxxxxxxxxxxxx(CHIPS) (MODULE:
TTCCI_VME; P~
ART: CAPCERSMDCL2)
#2 ERROR(101): Primitive
@TTCCI_LIB.TTCCI_TOP(SCH_1):PAGE1_I5@xxxxxxxxxxxxxx~
I_VME(SCH_1):PAGE1_I469@xxxxxxxxxxxxxxxxxxxxxx(CHIPS) is not packaged.
#3 ERROR(100): State file not written for design TTCCI_TOP.
And swaps (in the case of PN) are no more allowed (NO_SWAP_GATE properties
are attached to functions.
Does anybody know how to avoid this?
Thanks in advance.
William.
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------------------------------
Date: Tue, 18 Jan 2005 11:46:46 -0500
From: Mark Salberg <msalberg@xxxxxxxxxxxx>
Subject: [PCB_FORUM] Re: LOCATION feedback
Hello Gary,
The reason that we do not swap pins is because first of all the library
parts are not created as swappable I am told.
Secondly, doesn't Concept actually change the symbol (.body)?
Meaning that if pins 1234 were swapped to 1324 that the pin numbers
would swap in schematic, but NOT the pin names if only text?
And if the schematic .body was replaced or refreshed, would then be wrong.
Scary! Is this still the way it is?
I would love to swap pins, but this is the way it was described to me.
In the past, I had done it in other software that generated a WAS / IS
file and net list compare.
Thanks,
Mark
Gary MacIndoe wrote:
> William,
>
> This has been a real PITA for me for a long time now. After I do rpak
> swaps, the engineer (using Concept HDL) does an import physical, then
> an export physical to complete a full loop to make sure we are in
> sync. If things change and I want to redo the rpak swaps, this
> bothersome NO_SWAP_GATE property (sometimes also NO_SWAP_GATE_EXT is
> there) is on some of the rpak sections and I have to remove it before
> I can swap function again.
>
> We thought we had it figured out once but it turned out not to work
> (it looks like it should have worked!), in Program Manager:
>
> - load in your *.cpm file
>
> - click on Setup
>
> - in the Tools tab, click on Setup... next to Packager-XL
>
> - in the Properties tab, click on Property Flow Setup...
>
> - in the Name column, find NO_SWAP_GATE (and NO_SWAP_GATE_EXT)
>
> - click the box to remove the check in the Defined In Concept column
> for the above properties
>
> - OK out of the Program Manager Setup windows
>
>
> This should prevent Concept from reapplying the above properties, but
> it didn't work for us. We haven't tried it for a while, maybe it
> really works now!
>
> Good luck!
>
>
> Gary E. MacIndoe
> PCB Design Engineer
> Advanced Micro Devices, Inc.
> Longmont, Colorado
>
> -----Original Message-----
> From: William Billereau [mailto:william.billereau@xxxxxxx]
> Sent: Tuesday, January 18, 2005 3:20 AM
> To: icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] LOCATION feedback
>
> Hello All.
>
> The packager assigns, the first time it runs, $LOCATION on Concept
> parts.
>
> After component placement and swaps, we backannote them on the BRD
> and feedback changes to Concept.
> Then some $LOCATION are changed to LOCATION (not all, but
> especially component were swap pins or functions was made)
> The same thing occurs with $PN properties that become PN
>
> If you copy in the design a component with a LOCATION, it copies
> the whole property (name and value) to the copy and the next
> packaging will fail with such errors because of two instances of
> LOCATION:
> #1 ERROR(1109): Cannot package instance into package C59.
> Schematic instance:
> @TTCCI_LIB.TTCCI_TOP(SCH_1):PAGE1_I5@xxxxxxxxxxxxx~
> CI_VME(SCH_1):PAGE1_I469@xxxxxxxxxxxxxxxxxxxxxx(CHIPS) (MODULE:
> TTCCI_VME; PAR~
> T: CAPCERSMDCL2)
> Section 1 is assigned
> @TTCCI_LIB.TTCCI_TOP(SCH_1):PAGE1_I5@xxxxxxxxxxx~
> TCCI_VME(SCH_1):PAGE1_I143@xxxxxxxxxxxxxxxxxxxxxx(CHIPS) (MODULE:
> TTCCI_VME; P~
> ART: CAPCERSMDCL2)
> #2 ERROR(101): Primitive
> @TTCCI_LIB.TTCCI_TOP(SCH_1):PAGE1_I5@xxxxxxxxxxxxxx~
> I_VME(SCH_1):PAGE1_I469@xxxxxxxxxxxxxxxxxxxxxx(CHIPS) is not packaged.
> #3 ERROR(100): State file not written for design TTCCI_TOP.
>
> And swaps (in the case of PN) are no more allowed (NO_SWAP_GATE
> properties are attached to functions.
>
> Does anybody know how to avoid this?
>
> Thanks in advance.
>
> William.
>
>
>
>
> _____________________________________________________________________________
> Scanned by IBM Email Security Management Services powered by
> MessageLabs. For more information please visit http://www.ers.ibm.com
> _____________________________________________________________________________
_____________________________________________________________________________
Scanned by IBM Email Security Management Services powered by MessageLabs. For
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------------------------------
Subject: [PCB_FORUM] Unschedule a Group of User Scheduled Nets
Date: Tue, 18 Jan 2005 16:47:44 -0500
From: "Chris Brennan" <Chris.Brennan@xxxxxxxx>
Hi All. Does anyone know of a way to unschedule at large group (1000's)
of nets that have a user schedule on them? The only way I know of is to
use the net schedule command, select each net individually, then
right-click and select unschedule. This procedure is obviously very
painful when trying to unschedule a large number of nets.
Any takers?
Thanks,
CJB
Chris Brennan, C.I.D.
PCB Designer
Fidus Systems Inc.
------------------------------
From: "Todd Westerhoff (twesterh)" <twesterh@xxxxxxxxx>
Subject: [PCB_FORUM] Re: Unschedule a Group of User Scheduled Nets
Date: Tue, 18 Jan 2005 16:58:45 -0500
You can use the UNSCHEDULE command in a third party netlist. The simplest
way is to just use an incremental netlist with only the names of the nets
you want unscheduled; i.e.
$PACKAGES
$NETS
$UNSCHEDULE
'NET1'
'NET2'
'NET3'
'NET4'
$END
Todd.
Todd Westerhoff
High Speed Design Specialist
Cisco Systems
1414 Massachusetts Ave - Boxboro, MA - 01719
email:twesterh@xxxxxxxxx
ph: 978-936-2149
============================================
"Always do right.
This will gratify some people and astonish the rest."
- Mark Twain
-----Original Message-----
From: Chris Brennan [mailto:Chris.Brennan@xxxxxxxx]
Sent: Tuesday, January 18, 2005 4:48 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Unschedule a Group of User Scheduled Nets
Hi All. Does anyone know of a way to unschedule at large group (1000's) of
nets that have a user schedule on them? The only way I know of is to use
the net schedule command, select each net individually, then right-click and
select unschedule. This procedure is obviously very painful when trying to
unschedule a large number of nets.
Any takers?
Thanks,
CJB
Chris Brennan, C.I.D.
PCB Designer
Fidus Systems Inc.
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------------------------------
Subject: [PCB_FORUM] Testprep Problem
Date: Tue, 18 Jan 2005 16:26:35 -0600
From: "Carrow, Dennis P." <Dennis.Carrow@xxxxxxx>
Hello All,
I'm having a slight problem. I cannot get the Auto Testprep program to
assign testpoints. I have thru hole connectors that I want to test. It will
allow me to use 'Create Probe' and select an individual pin on the connector
but when I run the auto program it fails on all nets but one(anagnd). I have
attached the log file. Can someone tell me what I'm doing wrong? Thanks in
advance! (using 14.2)
<<testprep.log>>
-- Binary/unsupported file stripped by Ecartis --
-- Type: application/octet-stream
-- File: testprep.log
-- Desc: testprep.log
------------------------------
Subject: [PCB_FORUM] Re: Unschedule a Group of User Scheduled Nets
Date: Tue, 18 Jan 2005 17:28:31 -0500
In 15.2, you can unschedule by window.
Logic > Net Schedule > RMB > Unschedule then window around nets
Ed
Ed Hickey
Allegro Technical Marketing Manager
Cadence Design Systems
Chelmsford, MA 01824
978-262-6545
-----Original Message-----
From: Chris Brennan [mailto:Chris.Brennan@xxxxxxxx]
Sent: Tuesday, January 18, 2005 4:48 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Unschedule a Group of User Scheduled Nets
Hi All. Does anyone know of a way to unschedule at large group (1000's)
of nets that have a user schedule on them? The only way I know of is to
use the net schedule command, select each net individually, then
right-click and select unschedule. This procedure is obviously very
painful when trying to unschedule a large number of nets.
Any takers?
Thanks,
CJB
Chris Brennan, C.I.D.
PCB Designer
Fidus Systems Inc.
-----------------------------------------------------------
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------------------------------
Subject: [PCB_FORUM] Re: Unschedule a Group of User Scheduled Nets
Date: Tue, 18 Jan 2005 17:38:50 -0500
From: "Chris Brennan" <Chris.Brennan@xxxxxxxx>
Thanks Ed. Nice feature I didn't know about!!
Todd, your procedure worked well as well.
Thanks a bunch!
CJB
Chris Brennan, C.I.D.
PCB Designer
Fidus Systems Inc.
-----Original Message-----
From: MAILER-DAEMON@xxxxxxxxxxxxx [mailto:MAILER-DAEMON@xxxxxxxxxxxxx]
Sent: Tuesday, January 18, 2005 5:29 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Unschedule a Group of User Scheduled Nets
In 15.2, you can unschedule by window.
Logic > Net Schedule > RMB > Unschedule then window around nets
Ed
Ed Hickey
Allegro Technical Marketing Manager
Cadence Design Systems
Chelmsford, MA 01824
978-262-6545
-----Original Message-----
From: Chris Brennan [mailto:Chris.Brennan@xxxxxxxx]
Sent: Tuesday, January 18, 2005 4:48 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Unschedule a Group of User Scheduled Nets
Hi All. Does anyone know of a way to unschedule at large group (1000's)
of nets that have a user schedule on them? The only way I know of is to
use the net schedule command, select each net individually, then
right-click and select unschedule. This procedure is obviously very
painful when trying to unschedule a large number of nets.
Any takers?
Thanks,
CJB
Chris Brennan, C.I.D.
PCB Designer
Fidus Systems Inc.
-----------------------------------------------------------
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------------------------------
Date: Wed, 19 Jan 2005 12:03:58 +1300
From: "steve kingdon" <steve.kingdon@xxxxxxxxxxxxxxxxxxx>
Subject: [PCB_FORUM] Diff pair separation.
Hi there,
A "while" ago I used to be able to assign a net spacing type to diff
pairs which would keep the pairs apart, while allowing the primary gap
to be maintained.
I have assigned a net spacing type to all signals in my diff pair bus,
and find that I get line-line violations within the pairs, it is looking
for 40mil sep, which is the value I wanted for the pair to pair sep. Has
the way Allegro handles this changed, or has it been too long since I
did this last? I set up diff pairs in CM, on 15.2 s036.
I recall this came up a few months ago....
Cheers
Steve
---------------------------------------------------------------------------------
Steve Kingdon PCB Design Engineer
Allied Telesyn Research Level 2, 445 New North Rd
ph. 64 9 815 9824 Kingsland, Auckland
email: steve.kingdon@xxxxxxxxxxxxxxxxxxx
web: http://www.alliedtelesyn.co.nz/
----------------------------------------------------------------------------------
NOTICE: This message contains privileged and confidential
information intended only for the use of the addressee
named above. If you are not the intended recipient of
this message you are hereby notified that you must not
disseminate, copy or take any action in reliance on it.
If you have received this message in error please
notify Allied Telesyn Research Ltd immediately.
Any views expressed in this message are those of the
individual sender, except where the sender has the
authority to issue and specifically states them to
be the views of Allied Telesyn Research.
------------------------------
Subject: [PCB_FORUM] Re: Diff pair separation.
From: Michael.Catrambone@xxxxxxxxxx
Date: Tue, 18 Jan 2005 17:24:53 -0600
Steve,
For each of your diff pairs you must specify the Min Line Spacing
field in CM with the same value as your diff pair spacing.
This setting is a replacement for the old Diff_Pair_Overide variable
used in previous versions.
Hope this helps,
Michael Catrambone
UTStarcom, Inc.
"steve kingdon" <steve.kingdon
01/18/2005 05:03 PM
Please respond to icu-pcb-forum@xxxxxxxxxxxxx
Sent by:
To: <icu-pcb-forum@xxxxxxxxxxxxx>
cc:
Subject: [PCB_FORUM] Diff pair separation.
Hi there,
A "while" ago I used to be able to assign a net spacing type to diff
pairs which would keep the pairs apart, while allowing the primary gap
to be maintained.
I have assigned a net spacing type to all signals in my diff pair bus,
and find that I get line-line violations within the pairs, it is looking
for 40mil sep, which is the value I wanted for the pair to pair sep. Has
the way Allegro handles this changed, or has it been too long since I
did this last? I set up diff pairs in CM, on 15.2 s036.
I recall this came up a few months ago....
Cheers
Steve
---------------------------------------------------------------------------------
Steve Kingdon PCB Design Engineer
Allied Telesyn Research Level 2, 445 New North Rd
ph. 64 9 815 9824 Kingsland, Auckland
email: steve.kingdon@xxxxxxxxxxxxxxxxxxx
web: http://www.alliedtelesyn.co.nz/
----------------------------------------------------------------------------------
NOTICE: This message contains privileged and confidential
information intended only for the use of the addressee
named above. If you are not the intended recipient of
this message you are hereby notified that you must not
disseminate, copy or take any action in reliance on it.
If you have received this message in error please
notify Allied Telesyn Research Ltd immediately.
Any views expressed in this message are those of the
individual sender, except where the sender has the
authority to issue and specifically states them to
be the views of Allied Telesyn Research.
-----------------------------------------------------------
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------------------------------
Date: Wed, 19 Jan 2005 13:15:30 +1300
From: "steve kingdon" <steve.kingdon@xxxxxxxxxxxxxxxxxxx>
Subject: [PCB_FORUM] Re: Diff pair separation.
Yup, that was it. DRCs didn't automatically disappear, had to update
DRC.
Thanks a lot,
Steve
>>> Michael.Catrambone@xxxxxxxxxx 19/01/05 12:24:53 >>>
Steve,
For each of your diff pairs you must specify the Min Line Spacing
field in CM with the same value as your diff pair spacing.
This setting is a replacement for the old Diff_Pair_Overide variable
used in previous versions.
Hope this helps,
Michael Catrambone
UTStarcom, Inc.
"steve kingdon" <steve.kingdon
01/18/2005 05:03 PM
Please respond to icu-pcb-forum@xxxxxxxxxxxxx
Sent by:
To: <icu-pcb-forum@xxxxxxxxxxxxx>
cc:
Subject: [PCB_FORUM] Diff pair separation.
Hi there,
A "while" ago I used to be able to assign a net spacing type to diff
pairs which would keep the pairs apart, while allowing the primary gap
to be maintained.
I have assigned a net spacing type to all signals in my diff pair bus,
and find that I get line-line violations within the pairs, it is
looking
for 40mil sep, which is the value I wanted for the pair to pair sep.
Has
the way Allegro handles this changed, or has it been too long since I
did this last? I set up diff pairs in CM, on 15.2 s036.
I recall this came up a few months ago....
Cheers
Steve
---------------------------------------------------------------------------------
Steve Kingdon PCB Design Engineer
Allied Telesyn Research Level 2, 445 New North Rd
ph. 64 9 815 9824 Kingsland, Auckland
email: steve.kingdon@xxxxxxxxxxxxxxxxxxx
web: http://www.alliedtelesyn.co.nz/
----------------------------------------------------------------------------------
NOTICE: This message contains privileged and confidential
information intended only for the use of the addressee
named above. If you are not the intended recipient of
this message you are hereby notified that you must not
disseminate, copy or take any action in reliance on it.
If you have received this message in error please
notify Allied Telesyn Research Ltd immediately.
Any views expressed in this message are those of the
individual sender, except where the sender has the
authority to issue and specifically states them to
be the views of Allied Telesyn Research.
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-----------------------------------------------------------
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named above. If you are not the intended recipient of
this message you are hereby notified that you must not
disseminate, copy or take any action in reliance on it.
If you have received this message in error please
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Any views expressed in this message are those of the
individual sender, except where the sender has the
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be the views of Allied Telesyn Research.
------------------------------
Date: Wed, 19 Jan 2005 08:38:41 +0200
From: Michael Ben-atar <michael.ben-atar@xxxxxxxxxxxx>
Subject: [PCB_FORUM] multiple route
Hello eveyone
i'm using 15.1 allegro.
i would like to use multiple route by F6 .
this option doesn't work ,can someone tell me what i have to set on my
env to enable it.
michael
thank you
------------------------------
Date: Wed, 19 Jan 2005 07:52:09 -0500
From: Kevin McCowan <kmccowan@xxxxxxxxxxxxxx>
Subject: [PCB_FORUM] Re: Testprep Problem
It looks to me like you have a rules problem.
From what the log file says, anyway.
It says that if the pad is not defined on the bottom it is
too close to some other feature to allow it to place the
test pad.
Check your rules. Not just for the test points but
also all metal rules. You might want to set the test point
grid to something smaller than 10 mils. Maybe set
displacement to something larger than 0 to allow for
testpoint landing sites that don't fall on the grid.
Hope I'm right and this helps,
Kevin McCowan
Sr. PCB Designer
TSI Telsys
Carrow, Dennis P. wrote:
> Hello All,
> I'm having a slight problem. I cannot get the Auto Testprep
program to assign testpoints. I have thru hole connectors
that I
want to test. It will allow me to use 'Create Probe' and select
an individual pin on the connector but when I run the auto
program
it fails on all nets but one(anagnd). I have attached the
log file.
Can someone tell me what I'm doing wrong? Thanks in
advance! (using 14.2)
>
> <<testprep.log>>
------------------------------
Date: Wed, 19 Jan 2005 06:53:23 -0600
From: Richard Colston <richard.colston@xxxxxxxxxxx>
Subject: [PCB_FORUM] Re: Testprep Problem
Try changing your test grid to 0.00. The pins of your connector may be
less than .01 and so Testprep cannot use them, regardless of the spacing.
RAC
Carrow, Dennis P. wrote:
>Hello All,
> I'm having a slight problem. I cannot get the Auto Testprep program to
> assign testpoints. I have thru hole connectors that I want to test. It will
> allow me to use 'Create Probe' and select an individual pin on the connector
> but when I run the auto program it fails on all nets but one(anagnd). I have
> attached the log file. Can someone tell me what I'm doing wrong? Thanks in
> advance! (using 14.2)
>
> <<testprep.log>>
>
>
------------------------------
Subject: [PCB_FORUM] Re: Testprep Problem
Date: Wed, 19 Jan 2005 07:12:22 -0600
From: "Carrow, Dennis P." <Dennis.Carrow@xxxxxxx>
Got it! Thanks for all the replies! Actually it was someone else's problem
that I was asked to help out on. He had an anagnd plane on one layer that he
had neglected to void. Apparently, the drc's kept the Auto Probe program from
selecting those pins with drc's(but allowed Create Probe to work). I voided
the plane for a test and ran it again and low and behold all connector pins
became test points! Thanks again! -Dennis
-----Original Message-----
From: Kevin McCowan [mailto:kmccowan@xxxxxxxxxxxxxx]
Sent: Wednesday, January 19, 2005 6:52 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Testprep Problem
It looks to me like you have a rules problem.
From what the log file says, anyway.
It says that if the pad is not defined on the bottom it is
too close to some other feature to allow it to place the
test pad.
Check your rules. Not just for the test points but
also all metal rules. You might want to set the test point
grid to something smaller than 10 mils. Maybe set
displacement to something larger than 0 to allow for
testpoint landing sites that don't fall on the grid.
Hope I'm right and this helps,
Kevin McCowan
Sr. PCB Designer
TSI Telsys
Carrow, Dennis P. wrote:
> Hello All,
> I'm having a slight problem. I cannot get the Auto Testprep
program to assign testpoints. I have thru hole connectors
that I
want to test. It will allow me to use 'Create Probe' and select
an individual pin on the connector but when I run the auto
program
it fails on all nets but one(anagnd). I have attached the
log file.
Can someone tell me what I'm doing wrong? Thanks in
advance! (using 14.2)
>
> <<testprep.log>>
-----------------------------------------------------------
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POST: icu-jobs-forum@xxxxxxxxxx
-----------------------------------------------------------
------------------------------
Subject: [PCB_FORUM] Re: Testprep Problem
Date: Wed, 19 Jan 2005 10:10:26 -0500
For future reference .....
According to the testprep.log file Dennis attached, all the failures on
the nets are due to one of two different reasons:
'too-close=<n>' ... <n> points (e.g. pins or vias) failed because
they were either
too close to other already existing testpoints
(minimum spacing
of 5.00), OR in fact the testpoint would create
DRC errors. The
'too-close' category combines both situations.
'pad undef=<n>' ... <n> pin or via points on the net failed because
with BOTTOM side
testing enabled, the pin or via point does not
have a pad
existing on the BOTTOM side for probing.
Ed Hickey
Allegro Technical Marketing Manager
Cadence Design Systems
Chelmsford, MA 01824
978-262-6545
-----Original Message-----
From: Carrow, Dennis P. [mailto:Dennis.Carrow@xxxxxxx]
Sent: Wednesday, January 19, 2005 8:12 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Testprep Problem
Got it! Thanks for all the replies! Actually it was someone else's
problem that I was asked to help out on. He had an anagnd plane on one
layer that he had neglected to void. Apparently, the drc's kept the
Auto Probe program from selecting those pins with drc's(but allowed
Create Probe to work). I voided the plane for a test and ran it again
and low and behold all connector pins became test points! Thanks again!
-Dennis
-----Original Message-----
From: Kevin McCowan [mailto:kmccowan@xxxxxxxxxxxxxx]
Sent: Wednesday, January 19, 2005 6:52 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Testprep Problem
It looks to me like you have a rules problem.
From what the log file says, anyway.
It says that if the pad is not defined on the bottom it is too close to
some other feature to allow it to place the test pad.
Check your rules. Not just for the test points but also all metal rules.
You might want to set the test point grid to something smaller than 10
mils. Maybe set displacement to something larger than 0 to allow for
testpoint landing sites that don't fall on the grid.
Hope I'm right and this helps,
Kevin McCowan
Sr. PCB Designer
TSI Telsys
Carrow, Dennis P. wrote:
> Hello All,
> I'm having a slight problem. I cannot get the Auto Testprep
program to assign testpoints. I have thru hole connectors that I want
to test. It will allow me to use 'Create Probe' and select an
individual pin on the connector but when I run the auto program it fails
on all nets but one(anagnd). I have attached the log file.
Can someone tell me what I'm doing wrong? Thanks in advance! (using
14.2)
>
> <<testprep.log>>
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From: <sjcharles@xxxxxxx>
Subject: [PCB_FORUM] allegro to power pcb
Date: Wed, 19 Jan 2005 10:32:45 -0500
Group: Anyone tried to translate allegro pcb database to powerpcb?
------------------------------
Date: Wed, 19 Jan 2005 07:35:02 -0800 (PST)
From: Clyde Sprowl <pwb_engineer@xxxxxxxxx>
Subject: [PCB_FORUM] Re: allegro to power pcb
Why would you WANT to?
sjcharles@xxxxxxx wrote:Group: Anyone tried to translate allegro pcb database
to powerpcb?
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------------------------------
Date: Wed, 19 Jan 2005 10:42:59 -0500
From: SjChar3@xxxxxxxxxxxx
Subject: [PCB_FORUM] Re: allegro to power pcb
Someone wants our design, we use cadence but our sister group is hanging back
about switching to cadence. Some people just don't want to go with the flow.
Clyde Sprowl <pwb_engineer@xxxxxxxxx> wrote:
>Why would you WANT to?
>
>sjcharles@xxxxxxx wrote:Group: Anyone tried to translate allegro pcb database
>to powerpcb?
>
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Date: Wed, 19 Jan 2005 08:07:19 -0800 (PST)
From: Clyde Sprowl <pwb_engineer@xxxxxxxxx>
Subject: [PCB_FORUM] Re: allegro to power pcb
Bring them along gently, until they see the light, Grasshopper...
SjChar3@xxxxxxxxxxxx wrote:Someone wants our design, we use cadence but our
sister group is hanging back about switching to cadence. Some people just don't
want to go with the flow.
Clyde Sprowl
wrote:
>Why would you WANT to?
>
>sjcharles@xxxxxxx wrote:Group: Anyone tried to translate allegro pcb database
>to powerpcb?
>
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------------------------------
Date: Wed, 19 Jan 2005 09:10:11 -0800 (PST)
Subject: [PCB_FORUM] Re: allegro to power pcb
From: "Mitch S. Morey" <cadpro2k@xxxxxxxxxx>
Hi Sam,
The concensus seems to be that with PowerPCB the only way to get a
'cadence like' database is to output the gerbers, run them thru CAM350 and
import them to PowerPCB (PPCB doesn't import gerbers directly!). I've
heard the question asked about 3-5 times on the PPCB listserver, but there
doesn't seem to be an easy way. Since Allegro doesn't output an ascii
'database' per se, Mentor hasn't worked out the translation. Supposedly
there's a way to translate Allegro to Expedition, or is it AutoActiveRE?
From there you might be able to get it to PPCB, but I doubt it.
Good day.
Mitch
>
> Group: Anyone tried to translate allegro pcb database to powerpcb?
-----------------------------------------
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------------------------------
Subject: [PCB_FORUM] Re: allegro to power pcb
From: Andy_Kulik@xxxxxxx
Date: Wed, 19 Jan 2005 12:20:37 -0500
How many different PCB tools does Mentor offer?
Are there any customization capabilities such as Allegro Skill?
Andy
Mitch S. Morey
Sent by:
01/19/2005 12:10 PM
Please respond to
icu-pcb-forum@xxxxxxxxxxxxx
To
icu-pcb-forum@xxxxxxxxxxxxx
cc
Subject
[PCB_FORUM] Re: allegro to power pcb
Hi Sam,
The concensus seems to be that with PowerPCB the only way to get a
'cadence like' database is to output the gerbers, run them thru CAM350 and
import them to PowerPCB (PPCB doesn't import gerbers directly!). I've
heard the question asked about 3-5 times on the PPCB listserver, but there
doesn't seem to be an easy way. Since Allegro doesn't output an ascii
'database' per se, Mentor hasn't worked out the translation. Supposedly
there's a way to translate Allegro to Expedition, or is it AutoActiveRE?
From there you might be able to get it to PPCB, but I doubt it.
Good day.
Mitch
>
> Group: Anyone tried to translate allegro pcb database to powerpcb?
-----------------------------------------
Stay ahead of the information curve.
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------------------------------
From: "Dharma Kemp-Bresett" <dharma@xxxxxxx>
Subject: [PCB_FORUM] Re: allegro to power pcb
Date: Wed, 19 Jan 2005 12:17:58 -0500
Andy,
DXDesigner and Expedition have a VB front end.
Dharma
-----Original Message-----
From: Andy_Kulik@xxxxxxx [mailto:Andy_Kulik@xxxxxxx]
Sent: Wednesday, January 19, 2005 12:21 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: allegro to power pcb
How many different PCB tools does Mentor offer?
Are there any customization capabilities such as Allegro Skill?
Andy
Mitch S. Morey
Sent by:
01/19/2005 12:10 PM
Please respond to
icu-pcb-forum@xxxxxxxxxxxxx
To
icu-pcb-forum@xxxxxxxxxxxxx
cc
Subject
[PCB_FORUM] Re: allegro to power pcb
Hi Sam,
The concensus seems to be that with PowerPCB the only way to get a
'cadence like' database is to output the gerbers, run them thru CAM350 and
import them to PowerPCB (PPCB doesn't import gerbers directly!). I've
heard the question asked about 3-5 times on the PPCB listserver, but there
doesn't seem to be an easy way. Since Allegro doesn't output an ascii
'database' per se, Mentor hasn't worked out the translation. Supposedly
there's a way to translate Allegro to Expedition, or is it AutoActiveRE?
>From there you might be able to get it to PPCB, but I doubt it.
Good day.
Mitch
>
> Group: Anyone tried to translate allegro pcb database to powerpcb?
-----------------------------------------
Stay ahead of the information curve.
Receive PCB news and jobs on your desktop daily.
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-----------------------------------------------------------
------------------------------
Date: Wed, 19 Jan 2005 09:19:14 -0800 (PST)
Subject: [PCB_FORUM] Re: allegro to power pcb
From: "Mitch S. Morey" <cadpro2k@xxxxxxxxxx>
> How many different PCB tools does Mentor offer?
> Are there any customization capabilities such as Allegro Skill?
> Andy
>
Mentor Boardstation - High end (uses AMPLE code to customize)
Mentor Expedition - Mid tier (not sure there is customization)
Mentor PowerPCB - used to be PADS (uses VB scripts)
Mentor AutoActiveRE - much like the Specctra interactive router
Good day.
Mitch
-----------------------------------------
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It's informative and essential.
------------------------------
From: "Dave Schaefer" <dave.schaefer@xxxxxxx>
Subject: [PCB_FORUM] Re: allegro to power pcb
Date: Wed, 19 Jan 2005 11:19:48 -0600
Pads, RE, Boardstation, Expedition are all Mentor packages.
Boardstation has "Ample".
Dave Schaefer
<mailto:dave.schaefer@xxxxxxxxxxxx> dave.schaefer@xxxxxxxxxxxx
-----Original Message-----
From: Andy_Kulik@xxxxxxx [mailto:Andy_Kulik@xxxxxxx]
Sent: Wednesday, January 19, 2005 11:21 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: allegro to power pcb
How many different PCB tools does Mentor offer?
Are there any customization capabilities such as Allegro Skill?
Andy
Mitch S. Morey
Sent by:
01/19/2005 12:10 PM
Please respond to
icu-pcb-forum@xxxxxxxxxxxxx
To
icu-pcb-forum@xxxxxxxxxxxxx
cc
Subject
[PCB_FORUM] Re: allegro to power pcb
Hi Sam,
The concensus seems to be that with PowerPCB the only way to get a
'cadence like' database is to output the gerbers, run them thru CAM350 and
import them to PowerPCB (PPCB doesn't import gerbers directly!). I've
heard the question asked about 3-5 times on the PPCB listserver, but there
doesn't seem to be an easy way. Since Allegro doesn't output an ascii
'database' per se, Mentor hasn't worked out the translation. Supposedly
there's a way to translate Allegro to Expedition, or is it AutoActiveRE?
From there you might be able to get it to PPCB, but I doubt it.
Good day.
Mitch
>
> Group: Anyone tried to translate allegro pcb database to powerpcb?
-----------------------------------------
Stay ahead of the information curve.
Receive PCB news and jobs on your desktop daily.
Subscribe today to the PCB CafeNews newsletter.
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-----------------------------------------------------------
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-----------------------------------------------------------
------------------------------
Date: Wed, 19 Jan 2005 12:36:25 -0500
From: Kevin McCowan <kmccowan@xxxxxxxxxxxxxx>
Subject: [PCB_FORUM] Re: allegro to power pcb
Wrong group.
This is the Allegro group.
Ha. Ha.
Kevin McCowan
Andy_Kulik@xxxxxxx wrote:
>
> How many different PCB tools does Mentor offer?
> Are there any customization capabilities such as Allegro Skill?
> Andy
>
>
>
>
> *Mitch S. Morey*
> Sent by:
>
> 01/19/2005 12:10 PM
> Please respond to
> icu-pcb-forum@xxxxxxxxxxxxx
>
>
>
> To
> icu-pcb-forum@xxxxxxxxxxxxx
> cc
>
> Subject
> [PCB_FORUM] Re: allegro to power pcb
>
>
>
>
>
>
>
>
> Hi Sam,
>
> The concensus seems to be that with PowerPCB the only way to get a
> 'cadence like' database is to output the gerbers, run them thru CAM350 and
> import them to PowerPCB (PPCB doesn't import gerbers directly!). I've
> heard the question asked about 3-5 times on the PPCB listserver, but there
> doesn't seem to be an easy way. Since Allegro doesn't output an ascii
> 'database' per se, Mentor hasn't worked out the translation. Supposedly
> there's a way to translate Allegro to Expedition, or is it AutoActiveRE?
> From there you might be able to get it to PPCB, but I doubt it.
>
> Good day.
>
> Mitch
>
> >
> > Group: Anyone tried to translate allegro pcb database to powerpcb?
>
>
>
> -----------------------------------------
> Stay ahead of the information curve.
> Receive PCB news and jobs on your desktop daily.
> Subscribe today to the PCB CafeNews newsletter.
> [ http://www10.pcbcafe.com/nl/newsletter_subscribe.php ]
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> -----------------------------------------------------------
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>
------------------------------
From: "Shiffer, Diane" <DianeS@xxxxxxxxxx>
Subject: [PCB_FORUM] Re: allegro to power pcb
Date: Wed, 19 Jan 2005 09:42:14 -0800
It's been a while since I've done that, but I believe you have to buy a
third party translator. The company that I bought translation software from
is RSI Software: www.rsi-inc.com I don't know if they are still around.
Translating Gerber's from CAM350 requires the upgraded version of CAM350
that will allow you to do the conversion.
Diane
-----Original Message-----
From: sjcharles@xxxxxxx [mailto:sjcharles@xxxxxxx]
Sent: Wednesday, January 19, 2005 7:33 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] allegro to power pcb
Group: Anyone tried to translate allegro pcb database to powerpcb?
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-----------------------------------------------------------
------------------------------
Subject: [PCB_FORUM] Re: allegro to power pcb
From: Andy_Kulik@xxxxxxx
Date: Wed, 19 Jan 2005 12:47:35 -0500
;-), Anyone know of an Ample manual somewhere?
Kevin McCowan
Sent by:
01/19/2005 12:36 PM
Please respond to
icu-pcb-forum@xxxxxxxxxxxxx
To
icu-pcb-forum@xxxxxxxxxxxxx
cc
Subject
[PCB_FORUM] Re: allegro to power pcb
Wrong group.
This is the Allegro group.
Ha. Ha.
Kevin McCowan
Andy_Kulik@xxxxxxx wrote:
>
> How many different PCB tools does Mentor offer?
> Are there any customization capabilities such as Allegro Skill?
> Andy
>
>
>
>
> *Mitch S. Morey*
> Sent by:
>
> 01/19/2005 12:10 PM
> Please respond to
> icu-pcb-forum@xxxxxxxxxxxxx
>
>
>
> To
> icu-pcb-forum@xxxxxxxxxxxxx
> cc
>
> Subject
> [PCB_FORUM] Re: allegro to power pcb
>
>
>
>
>
>
>
>
> Hi Sam,
>
> The concensus seems to be that with PowerPCB the only way to get a
> 'cadence like' database is to output the gerbers, run them thru CAM350
and
> import them to PowerPCB (PPCB doesn't import gerbers directly!). I've
> heard the question asked about 3-5 times on the PPCB listserver, but
there
> doesn't seem to be an easy way. Since Allegro doesn't output an ascii
> 'database' per se, Mentor hasn't worked out the translation. Supposedly
> there's a way to translate Allegro to Expedition, or is it AutoActiveRE?
> From there you might be able to get it to PPCB, but I doubt it.
>
> Good day.
>
> Mitch
>
> >
> > Group: Anyone tried to translate allegro pcb database to powerpcb?
>
>
>
> -----------------------------------------
> Stay ahead of the information curve.
> Receive PCB news and jobs on your desktop daily.
> Subscribe today to the PCB CafeNews newsletter.
> [ http://www10.pcbcafe.com/nl/newsletter_subscribe.php ]
> It's informative and essential.
> -----------------------------------------------------------
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-----------------------------------------------------------
------------------------------
Date: Wed, 19 Jan 2005 13:13:55 -0500
From: SjChar3@xxxxxxxxxxxx
Subject: [PCB_FORUM] Re: allegro to power pcb
thanks for input, been a long time since using RSI.
"Shiffer, Diane" <DianeS@xxxxxxxxxx> wrote:
>It's been a while since I've done that, but I believe you have to buy a
>third party translator. The company that I bought translation software from
>is RSI Software: www.rsi-inc.com I don't know if they are still around.
>Translating Gerber's from CAM350 requires the upgraded version of CAM350
>that will allow you to do the conversion.
>
>Diane
>
>-----Original Message-----
>From: sjcharles@xxxxxxx [mailto:sjcharles@xxxxxxx]
>Sent: Wednesday, January 19, 2005 7:33 AM
>To: icu-pcb-forum@xxxxxxxxxxxxx
>Subject: [PCB_FORUM] allegro to power pcb
>
>
>Group: Anyone tried to translate allegro pcb database to powerpcb?
>
>-----------------------------------------------------------
>To subscribe/unsubscribe:
> Send a message to icu-pcb-forum-request@xxxxxxxxxxxxx
> with a subject of subscribe or unsubscribe
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>or go to http://www.freelists.org/archives/icu-pcb-forum/
>
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From: "Shiffer, Diane" <DianeS@xxxxxxxxxx>
Subject: [PCB_FORUM] Re: allegro to power pcb
Date: Wed, 19 Jan 2005 10:39:55 -0800
Sure. Good luck.
-----Original Message-----
From: SjChar3@xxxxxxxxxxxx [mailto:SjChar3@xxxxxxxxxxxx]
Sent: Wednesday, January 19, 2005 10:14 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: allegro to power pcb
thanks for input, been a long time since using RSI.
"Shiffer, Diane" <DianeS@xxxxxxxxxx> wrote:
>It's been a while since I've done that, but I believe you have to buy a
>third party translator. The company that I bought translation software from
>is RSI Software: www.rsi-inc.com I don't know if they are still around.
>Translating Gerber's from CAM350 requires the upgraded version of CAM350
>that will allow you to do the conversion.
>
>Diane
>
>-----Original Message-----
>From: sjcharles@xxxxxxx [mailto:sjcharles@xxxxxxx]
>Sent: Wednesday, January 19, 2005 7:33 AM
>To: icu-pcb-forum@xxxxxxxxxxxxx
>Subject: [PCB_FORUM] allegro to power pcb
>
>
>Group: Anyone tried to translate allegro pcb database to powerpcb?
>
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------------------------------
Date: Thu, 20 Jan 2005 09:19:08 -0500
From: Dave Seymour <dave.seymour@xxxxxxxxxxxx>
Subject: [PCB_FORUM] Pads Netlist - 2- Allegro netlist
I have a PADs ascii text style netlist out of a shareware
schematic package, which doesn't output *.tel.
Does anyone know of a little text convertor routine that
can take the PADs netlist in and output an Allegro 3rd party netlist?
I have a couple of options, this would be the shorted path.
Thanks
dave
--
Dave Seymour, CID+
Catapult Communications Inc.
800 Perimeter Park Dr, Suite A
Morrisville, NC 27560
Direct: (919)653-4249
Main: (919)653-4180
Fax: (919)653-4297
Dave.seymour@xxxxxxxxxxxx
------------------------------
Date: Thu, 20 Jan 2005 11:37:39 -0500
From: Kevin McCowan <kmccowan@xxxxxxxxxxxxxx>
Subject: [PCB_FORUM] Re: multiple route
I am curious.
Did you find a solution to this?
I tried to figure it out back when we had maintenance and
my cadence guy did not understand what I was asking.
Our maintenance ran out (a long story) and I never did
get an answer. I used the multi-route in Expedition
and it worked kinda ok. I would like to try it in
Allegro but, like you, could not get it to work.
Or, anyone else?
Thanks,
Kevin McCowan
Sr. PCB Designer
TSI Telsys
Michael Ben-atar wrote:
> Hello eveyone
> i'm using 15.1 allegro.
> i would like to use multiple route by F6 .
> this option doesn't work ,can someone tell me what i have to set on my
> env to enable it.
>
> michael
> thank you
>
> -----------------------------------------------------------
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------------------------------
From: "Joe Witten" <joe.witten@xxxxxxxxxxx>
Subject: [PCB_FORUM] Re: multiple route
Date: Thu, 20 Jan 2005 08:55:27 -0800
Sorry for the ignorance here, but is multiple route the same as bus routing?
If so, here is what we used in version 14.x.
Setting the environmental variable "acon_oldcmd" will
restore the 13.X interactive routing functionality in Allegro 14.X.
set acon_oldcmd
The "Route Type" under the Options tab should be set to
"To Cursor" in order to group clines to route as a bus.
I don't have version 15.1 installed to test it and 15.2 has this function
restored.
-----Original Message-----
From: Kevin McCowan [mailto:kmccowan@xxxxxxxxxxxxxx]
Sent: Thursday, January 20, 2005 8:38 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: multiple route
I am curious.
Did you find a solution to this?
I tried to figure it out back when we had maintenance and
my cadence guy did not understand what I was asking.
Our maintenance ran out (a long story) and I never did
get an answer. I used the multi-route in Expedition
and it worked kinda ok. I would like to try it in
Allegro but, like you, could not get it to work.
Or, anyone else?
Thanks,
Kevin McCowan
Sr. PCB Designer
TSI Telsys
Michael Ben-atar wrote:
> Hello eveyone
> i'm using 15.1 allegro.
> i would like to use multiple route by F6 .
> this option doesn't work ,can someone tell me what i have to set on
> my env to enable it.
>
> michael
> thank you
>
> -----------------------------------------------------------
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------------------------------
Date: Thu, 20 Jan 2005 12:02:15 -0500
From: rjbzxr@xxxxxxxxxxxx
Subject: [PCB_FORUM] Re: multiple route
Kevin, can you explain how Expedition handles multi-route ?
Do you mean something like Bus routing ? 15.2 supports bus routing you can just
go into the route command and widow over multiple tracks and route them
together ?
A bit more info on what your trying to achive would be helpful.
The Expedition datasheet only talks about : Multi-pass autorouting control
support.. which does things like diff pair and bus routing..
Kevin McCowan <kmccowan@xxxxxxxxxxxxxx> wrote:
>I am curious.
>Did you find a solution to this?
>I tried to figure it out back when we had maintenance and
>my cadence guy did not understand what I was asking.
>Our maintenance ran out (a long story) and I never did
>get an answer. I used the multi-route in Expedition
>and it worked kinda ok. I would like to try it in
>Allegro but, like you, could not get it to work.
>Or, anyone else?
>
>Thanks,
>Kevin McCowan
>Sr. PCB Designer
>TSI Telsys
>
>Michael Ben-atar wrote:
>> Hello eveyone
>> i'm using 15.1 allegro.
>> i would like to use multiple route by F6 .
>> this option doesn't work ,can someone tell me what i have to set on my
>> env to enable it.
>>
>> michael
>> thank you
>>
>> -----------------------------------------------------------
>> To subscribe/unsubscribe:
>> Send a message to icu-pcb-forum-request@xxxxxxxxxxxxx
>> with a subject of subscribe or unsubscribe
>>
>> To view the archives of this list please login at
>> http://www.freelists.org. Our list name is icu-pcb-forum
>> or go to http://www.freelists.org/archives/icu-pcb-forum/
>>
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>> Send an email to icu-pcb-forum-admins@xxxxxxxxxxxxx
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>> Better yet, join our jobs listing forum.
>>
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Subject: [PCB_FORUM] Re: multiple route
Date: Thu, 20 Jan 2005 09:07:41 -0800
From: "Rix, Randy B" <randy.b.rix@xxxxxxxxx>
I don't know what your F6 function key was defined as, but here is a
workaround that Cadence helped us with a while back. It works in 14.2;
don't know about 15.1. FYI, 15.2 has a much better multi-route
capability.
1) Ensure all clines to be routed end at the same horizontal or vertial
coordinate and there aren't any obstacles in the route path.
2) Type "set acon_oldcmd"
3) On options tab:
- set active layer
- set route type to "To cursor"
4) Click and drag cursor to create a box that covers the end of the
lines.
5) When done, type "unset acon_oldcmd"
Hope this helps.
-Randy
My opinion's my own, not my company's.
-----Original Message-----
From: Kevin McCowan [mailto:kmccowan@xxxxxxxxxxxxxx]
Sent: Thursday, January 20, 2005 8:38 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: multiple route
I am curious.
Did you find a solution to this?
I tried to figure it out back when we had maintenance and my cadence guy
did not understand what I was asking.
Our maintenance ran out (a long story) and I never did get an answer. I
used the multi-route in Expedition and it worked kinda ok. I would like
to try it in Allegro but, like you, could not get it to work.
Or, anyone else?
Thanks,
Kevin McCowan
Sr. PCB Designer
TSI Telsys
Michael Ben-atar wrote:
> Hello eveyone
> i'm using 15.1 allegro.
> i would like to use multiple route by F6 .
> this option doesn't work ,can someone tell me what i have to set on
> my env to enable it.
>
> michael
> thank you
>
> -----------------------------------------------------------
> To subscribe/unsubscribe:
> Send a message to icu-pcb-forum-request@xxxxxxxxxxxxx
> with a subject of subscribe or unsubscribe
>
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>
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> Send an email to icu-pcb-forum-admins@xxxxxxxxxxxxx
>
> Want to post a job listing ? DON'T DO IT HERE!
> Better yet, join our jobs listing forum.
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------------------------------
Date: Thu, 20 Jan 2005 17:12:26 +0000
From: rjbzxr@xxxxxxxxxxxx
Subject: [PCB_FORUM] Re: multiple route
I'm with you Joe ;-)
I did a search on Google and Yahoo for "mutiple routing" and it came up with
Channel routing.. So basically Bus Routing..
** More info at the start would have helped..
http://www.coppercad.com/Channel_Routing.pdf#search='multiple%20routing%20pcb'
"Joe Witten" <joe.witten@xxxxxxxxxxx> wrote:
>Sorry for the ignorance here, but is multiple route the same as bus routing?
>If so, here is what we used in version 14.x.
>
>Setting the environmental variable "acon_oldcmd" will
>restore the 13.X interactive routing functionality in Allegro 14.X.
>
>set acon_oldcmd
>
>The "Route Type" under the Options tab should be set to
>"To Cursor" in order to group clines to route as a bus.
>
>
>I don't have version 15.1 installed to test it and 15.2 has this function
>restored.
>
>
>-----Original Message-----
>From: Kevin McCowan [mailto:kmccowan@xxxxxxxxxxxxxx]
>Sent: Thursday, January 20, 2005 8:38 AM
>To: icu-pcb-forum@xxxxxxxxxxxxx
>Subject: [PCB_FORUM] Re: multiple route
>
>
>I am curious.
>Did you find a solution to this?
>I tried to figure it out back when we had maintenance and
>my cadence guy did not understand what I was asking.
>Our maintenance ran out (a long story) and I never did
>get an answer. I used the multi-route in Expedition
>and it worked kinda ok. I would like to try it in
>Allegro but, like you, could not get it to work.
>Or, anyone else?
>
>Thanks,
>Kevin McCowan
>Sr. PCB Designer
>TSI Telsys
>
>Michael Ben-atar wrote:
>> Hello eveyone
>> i'm using 15.1 allegro.
>> i would like to use multiple route by F6 .
>> this option doesn't work ,can someone tell me what i have to set on
>> my env to enable it.
>>
>> michael
>> thank you
>>
>> -----------------------------------------------------------
>> To subscribe/unsubscribe:
>> Send a message to icu-pcb-forum-request@xxxxxxxxxxxxx
>> with a subject of subscribe or unsubscribe
>>
>> To view the archives of this list please login at
>> http://www.freelists.org. Our list name is icu-pcb-forum or go to
>> http://www.freelists.org/archives/icu-pcb-forum/
>>
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>> Send an email to icu-pcb-forum-admins@xxxxxxxxxxxxx
>>
>> Want to post a job listing ? DON'T DO IT HERE!
>> Better yet, join our jobs listing forum.
>>
>> SUBSCRIBE: icu-jobs-forum-subscribe@xxxxxxxxxx
>> POST: icu-jobs-forum@xxxxxxxxxx
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From: "Schwartz, Jerome" <jschwa01@xxxxxxxxxx>
Subject: [PCB_FORUM] Re: multiple route
Date: Thu, 20 Jan 2005 12:17:45 -0500
Content-Type: text/plain
Kevin,
I just grab all the pins/vias I want to route by windowing them.
Then hit my right mouse button for options.
Regards,
Jerry Schwartz, CID+
IPC Advanced Certified Designer
"May The Schwartz Be With You."
Designer 3
Harris Corporation GCSD Voice (321)-727-5474
P.O. Box 37, MS 1/3232 Pager (321)-690-9797
Melbourne, FL 32902-0037
<mailto:Jerome.Schwartz@xxxxxxxxxx> mailto:Jerome.Schwartz@xxxxxxxxxx
<http://www.harris.com/> http://www.harris.com
-----Original Message-----
From: Kevin McCowan [mailto:kmccowan@xxxxxxxxxxxxxx
<mailto:kmccowan@xxxxxxxxxxxxxx> ]
Sent: Thursday, January 20, 2005 11:38 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: multiple route
I am curious.
Did you find a solution to this?
I tried to figure it out back when we had maintenance and
my cadence guy did not understand what I was asking.
Our maintenance ran out (a long story) and I never did
get an answer. I used the multi-route in Expedition
and it worked kinda ok. I would like to try it in
Allegro but, like you, could not get it to work.
Or, anyone else?
Thanks,
Kevin McCowan
Sr. PCB Designer
TSI Telsys
Michael Ben-atar wrote:
> Hello eveyone
> i'm using 15.1 allegro.
> i would like to use multiple route by F6 .
> this option doesn't work ,can someone tell me what i have to set on
> my env to enable it.
>
> michael
> thank you
>
> -----------------------------------------------------------
> To subscribe/unsubscribe:
> Send a message to icu-pcb-forum-request@xxxxxxxxxxxxx
> with a subject of subscribe or unsubscribe
>
> To view the archives of this list please login at
> http://www.freelists.org <http://www.freelists.org> . Our list name is
icu-pcb-forum or go to
> http://www.freelists.org/archives/icu-pcb-forum/
<http://www.freelists.org/archives/icu-pcb-forum/>
>
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