[PCB_FORUM] apply constraints to net portion of xnet only

Hello group,

 

I would like to know how you are handling this situation.

 

I would like the ability of adding different constraints on the nets
that form an xnet.  I was told by Cadence that this ability does not
exist as of today.    

 

In one case, prior to xnets being defined, I had a TOTAL_ETCH_LENGTH
property attached to one leg of a soon to be defined xnet.  The purpose
of this was to force the placement of a series termination resistor.
Once the xnet was defined, that same etch length property got propagated
to the entire xnet causing a DRC.

 

It appears that the xnet  gets its name from one of the nets that makes
up the xnet.  I do not know the algorithm in how it chooses to name the
xnet.  It seems to me what is needed is an xnet name that is unique.

 

Do you have any suggestions?

 

Thanks,

 

Chris

 

P.S.  here is a snippet from my case with Cadence

"The ability of adding different constraints on the nets that form an
xnet doesnt exist as of today.  There is an already existing Enhancement
PCR 811652 Title : apply constraints to net portion of xnet only
regarding this issue. I will append your SR to this PCR."

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