[PCB_FORUM] Re: a design reuse question

Are you sure that your gen_subdesign gets set all of the time?
Believe that you need the updated state file to bring all of the
parts in. If not set you could be using an old packager state file.

Mike
 

-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Rock Shi
Sent: Tuesday, November 22, 2005 1:28 PM
To: 'icu-pcb-forum@xxxxxxxxxxxxx'
Subject: [PCB_FORUM] Re: a design reuse question

Hi Mike,

I don't think that's the case, because the .mdd file was just re-created 
before I called it into the up level design.

Things really make me unhappy are each time I re-packagge, re-create 
module, and then re-use the module, there are always two parts missing 
from placement, but the parts changed from one trial to another!

I need more help. Thanks.

Best regards,

Rock

On Tue, 22 Nov 2005, gnieski, mike wrote:

>       Sounds like a disconnect between your schematic and module.
>       Possibly they are not in sync. Parts were removed on the
>       schematic and the .mdd was not updated?
>
>       Mike Gnieski
>       EMC Corp.
>
>
> -----Original Message-----
> From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
> [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Rock Shi
> Sent: Tuesday, November 22, 2005 12:33 PM
> To: icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] a design reuse question
>
> Hi,
>
> When I place a module for a subdesign into the layout for the top level
> design, some parts of the module will not be placed. Can anyone tell me
> why this could happen? I am using Allegro PCB15.2. Thanks.
>
> Best regards,
>
> Rock
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