[PCB_FORUM] Z-Axis Voltage spacing for adjacent layers?

Good morning,

Q.1 Is there any way to check for Z-axis (adjacent layer) voltage spacing DRC's?
We had a board arc with 240v potential between two inner layers with a dielectric thickness of 4mil.

According to IPC, V-spacing table we need 8mil (inner layer) 15mil (outer layer) spacing for 240V. (x,y & z axis)
Q.2. If the potential was from top layer and layer 2, should we use the 8mil or 15mil spacing?

Note: We are using Allegro v.15.1.

Thanks,
Mark


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